Lines Matching +full:fiq +full:- +full:index
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on irq-lpc32xx:
6 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
7 * Based on irq-bcm2836:
14 * - 896 level-triggered hardware IRQs
15 * - Single mask bit per IRQ
16 * - Per-IRQ affinity setting
17 * - Automatic masking on event delivery (auto-ack)
18 * - Software triggering (ORed with hw line)
19 * - 2 per-CPU IPIs (meant as "self" and "other", but they are
21 * - Automatic prioritization (single event/ack register per CPU, lower IRQs =
23 * - Automatic masking on ack
24 * - Default "this CPU" register view and explicit per-CPU views
32 * - This driver creates two IRQ domains, one for HW IRQs and internal FIQs,
34 * - Since Linux needs more than 2 IPIs, we implement a software IRQ controller
35 * and funnel all IPIs into one per-CPU IPI (the second "self" IPI is unused).
36 * - FIQ hwirq numbers are assigned after true hwirqs, and are per-cpu.
37 * - DT bindings use 3-cell form (like GIC):
38 * - <0 nr flags> - hwirq #nr
39 * - <1 nr flags> - FIQ #nr
40 * - nr=0 Physical HV timer
41 * - nr=1 Virtual HV timer
42 * - nr=2 Physical guest timer
43 * - nr=3 Virtual guest timer
53 #include <linux/irqchip/arm-vgic-info.h>
65 #include <dt-bindings/interrupt-controller/apple-aic.h>
153 * forward-compatible.
163 * IMP-DEF sysregs that control FIQ sources
182 /* Guest timer FIQ enable register */
216 * FIQ hwirq index definitions: FIQ sources use the DT binding defines
225 /* Must be ordered as in apple-aic.h */
298 .compatible = "apple,t8103-aic",
302 .compatible = "apple,t8015-aic",
340 return readl_relaxed(ic->base + reg); in aic_ic_read()
345 writel_relaxed(val, ic->base + reg); in aic_ic_write()
357 u32 off = AIC_HWIRQ_DIE(hwirq) * ic->info.die_stride; in aic_irq_mask()
360 aic_ic_write(ic, ic->info.mask_set + off + MASK_REG(irq), MASK_BIT(irq)); in aic_irq_mask()
368 u32 off = AIC_HWIRQ_DIE(hwirq) * ic->info.die_stride; in aic_irq_unmask()
371 aic_ic_write(ic, ic->info.mask_clr + off + MASK_REG(irq), MASK_BIT(irq)); in aic_irq_unmask()
394 event = readl(ic->event + ic->info.event); in aic_handle_irq()
399 generic_handle_domain_irq(aic_irqc->hw_domain, event); in aic_handle_irq()
414 generic_handle_domain_irq(aic_irqc->hw_domain, in aic_handle_irq()
432 BUG_ON(!ic->info.target_cpu); in aic_irq_set_affinity()
439 aic_ic_write(ic, ic->info.target_cpu + AIC_HWIRQ_IRQ(hwirq) * 4, BIT(cpu)); in aic_irq_set_affinity()
451 return (type == IRQ_TYPE_LEVEL_HIGH || type == IRQ_TYPE_EDGE_RISING) ? 0 : -EINVAL; in aic_irq_set_type()
472 * FIQ irqchip
541 * the FIQ source state without having to peek down into sources... in aic_handle_fiq()
545 * - Fast IPIs (not yet used) in aic_handle_fiq()
546 * - The 4 timers (CNTP, CNTV for each of HV and guest) in aic_handle_fiq()
547 * - Per-core PMCs (not yet supported) in aic_handle_fiq()
548 * - Per-cluster uncore PMCs (not yet supported) in aic_handle_fiq()
550 * Since not dealing with any of these results in a FIQ storm, in aic_handle_fiq()
559 generic_handle_domain_irq(aic_irqc->hw_domain, in aic_handle_fiq()
563 generic_handle_domain_irq(aic_irqc->hw_domain, in aic_handle_fiq()
571 generic_handle_domain_irq(aic_irqc->hw_domain, in aic_handle_fiq()
576 generic_handle_domain_irq(aic_irqc->hw_domain, in aic_handle_fiq()
583 &aic_irqc->fiq_aff[AIC_CPU_PMU_P]->aff)) in aic_handle_fiq()
587 generic_handle_domain_irq(aic_irqc->hw_domain, in aic_handle_fiq()
595 pr_err_ratelimited("Uncore PMC FIQ fired. Masking.\n"); in aic_handle_fiq()
603 return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL; in aic_fiq_set_type()
607 .name = "AIC-FIQ",
622 struct aic_irq_chip *ic = id->host_data; in aic_irq_domain_map()
626 if (ic->info.version == 2) in aic_irq_domain_map()
630 irq_domain_set_info(id, irq, hw, chip, id->host_data, in aic_irq_domain_map()
634 int fiq = FIELD_GET(AIC_EVENT_NUM, hw); in aic_irq_domain_map() local
636 switch (fiq) { in aic_irq_domain_map()
639 irq_set_percpu_devid_partition(irq, &ic->fiq_aff[fiq]->aff); in aic_irq_domain_map()
646 irq_domain_set_info(id, irq, hw, &fiq_chip, id->host_data, in aic_irq_domain_map()
658 struct aic_irq_chip *ic = id->host_data; in aic_irq_domain_translate()
662 if (fwspec->param_count < 3 || fwspec->param_count > 4 || in aic_irq_domain_translate()
663 !is_of_node(fwspec->fwnode)) in aic_irq_domain_translate()
664 return -EINVAL; in aic_irq_domain_translate()
666 args = &fwspec->param[1]; in aic_irq_domain_translate()
668 if (fwspec->param_count == 4) { in aic_irq_domain_translate()
673 switch (fwspec->param[0]) { in aic_irq_domain_translate()
675 if (die >= ic->nr_die) in aic_irq_domain_translate()
676 return -EINVAL; in aic_irq_domain_translate()
677 if (args[0] >= ic->nr_irq) in aic_irq_domain_translate()
678 return -EINVAL; in aic_irq_domain_translate()
683 return -EINVAL; in aic_irq_domain_translate()
685 return -EINVAL; in aic_irq_domain_translate()
689 * In EL1 the non-redirected registers are the guest's, in aic_irq_domain_translate()
702 return -ENOENT; in aic_irq_domain_translate()
709 return -EINVAL; in aic_irq_domain_translate()
817 return -ENODEV; in aic_init_smp()
826 /* Mask all hard-wired per-CPU IRQ/FIQ sources */ in aic_init_cpu()
836 /* EL2-only (VHE mode) IRQ sources */ in aic_init_cpu()
846 /* PMC FIQ */ in aic_init_cpu()
850 /* Uncore PMC FIQ */ in aic_init_cpu()
859 if (aic_irqc->info.version == 1) { in aic_init_cpu()
868 * Always keep IPIs unmasked at the hardware level (except auto-masking in aic_init_cpu()
896 u32 fiq; in build_fiq_affinity() local
898 if (of_property_read_u32(aff, "apple,fiq-index", &fiq) || in build_fiq_affinity()
899 WARN_ON(fiq >= AIC_NR_FIQ) || ic->fiq_aff[fiq]) in build_fiq_affinity()
906 ic->fiq_aff[fiq] = kzalloc(sizeof(*ic->fiq_aff[fiq]), GFP_KERNEL); in build_fiq_affinity()
907 if (!ic->fiq_aff[fiq]) in build_fiq_affinity()
927 cpumask_set_cpu(cpu, &ic->fiq_aff[fiq]->aff); in build_fiq_affinity()
942 return -EIO; in aic_of_ic_init()
947 return -ENOMEM; in aic_of_ic_init()
950 irqc->base = regs; in aic_of_ic_init()
956 irqc->info = *(struct aic_info *)match->data; in aic_of_ic_init()
960 switch (irqc->info.version) { in aic_of_ic_init()
965 irqc->nr_irq = FIELD_GET(AIC_INFO_NR_IRQ, info); in aic_of_ic_init()
966 irqc->max_irq = AIC_MAX_IRQ; in aic_of_ic_init()
967 irqc->nr_die = irqc->max_die = 1; in aic_of_ic_init()
969 off = start_off = irqc->info.target_cpu; in aic_of_ic_init()
970 off += sizeof(u32) * irqc->max_irq; /* TARGET_CPU */ in aic_of_ic_init()
972 irqc->event = irqc->base; in aic_of_ic_init()
982 irqc->nr_irq = FIELD_GET(AIC2_INFO1_NR_IRQ, info1); in aic_of_ic_init()
983 irqc->max_irq = FIELD_GET(AIC2_INFO3_MAX_IRQ, info3); in aic_of_ic_init()
984 irqc->nr_die = FIELD_GET(AIC2_INFO1_LAST_DIE, info1) + 1; in aic_of_ic_init()
985 irqc->max_die = FIELD_GET(AIC2_INFO3_MAX_DIE, info3); in aic_of_ic_init()
987 off = start_off = irqc->info.irq_cfg; in aic_of_ic_init()
988 off += sizeof(u32) * irqc->max_irq; /* IRQ_CFG */ in aic_of_ic_init()
990 irqc->event = of_iomap(node, 1); in aic_of_ic_init()
991 if (WARN_ON(!irqc->event)) in aic_of_ic_init()
998 irqc->info.sw_set = off; in aic_of_ic_init()
999 off += sizeof(u32) * (irqc->max_irq >> 5); /* SW_SET */ in aic_of_ic_init()
1000 irqc->info.sw_clr = off; in aic_of_ic_init()
1001 off += sizeof(u32) * (irqc->max_irq >> 5); /* SW_CLR */ in aic_of_ic_init()
1002 irqc->info.mask_set = off; in aic_of_ic_init()
1003 off += sizeof(u32) * (irqc->max_irq >> 5); /* MASK_SET */ in aic_of_ic_init()
1004 irqc->info.mask_clr = off; in aic_of_ic_init()
1005 off += sizeof(u32) * (irqc->max_irq >> 5); /* MASK_CLR */ in aic_of_ic_init()
1006 off += sizeof(u32) * (irqc->max_irq >> 5); /* HW_STATE */ in aic_of_ic_init()
1008 if (!irqc->info.fast_ipi) in aic_of_ic_init()
1011 if (!irqc->info.local_fast_ipi) in aic_of_ic_init()
1014 irqc->info.die_stride = off - start_off; in aic_of_ic_init()
1016 irqc->hw_domain = irq_domain_create_tree(of_node_to_fwnode(node), in aic_of_ic_init()
1018 if (WARN_ON(!irqc->hw_domain)) in aic_of_ic_init()
1021 irq_domain_update_bus_token(irqc->hw_domain, DOMAIN_BUS_WIRED); in aic_of_ic_init()
1039 for (die = 0; die < irqc->nr_die; die++) { in aic_of_ic_init()
1040 for (i = 0; i < BITS_TO_U32(irqc->nr_irq); i++) in aic_of_ic_init()
1041 aic_ic_write(irqc, irqc->info.mask_set + off + i * 4, U32_MAX); in aic_of_ic_init()
1042 for (i = 0; i < BITS_TO_U32(irqc->nr_irq); i++) in aic_of_ic_init()
1043 aic_ic_write(irqc, irqc->info.sw_clr + off + i * 4, U32_MAX); in aic_of_ic_init()
1044 if (irqc->info.target_cpu) in aic_of_ic_init()
1045 for (i = 0; i < irqc->nr_irq; i++) in aic_of_ic_init()
1046 aic_ic_write(irqc, irqc->info.target_cpu + off + i * 4, 1); in aic_of_ic_init()
1047 off += irqc->info.die_stride; in aic_of_ic_init()
1050 if (irqc->info.version == 2) { in aic_of_ic_init()
1064 "irqchip/apple-aic/ipi:starting", in aic_of_ic_init()
1085 irqc->nr_irq, irqc->max_irq, irqc->nr_die, irqc->max_die, AIC_NR_FIQ, AIC_NR_SWIPI); in aic_of_ic_init()
1090 irq_domain_remove(irqc->hw_domain); in aic_of_ic_init()
1092 if (irqc->event && irqc->event != irqc->base) in aic_of_ic_init()
1093 iounmap(irqc->event); in aic_of_ic_init()
1094 iounmap(irqc->base); in aic_of_ic_init()
1096 return -ENODEV; in aic_of_ic_init()