Lines Matching +full:fiq +full:- +full:index
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
22 - Automatic masking on event delivery (auto-ack)
23 - Software triggering (ORed with hw line)
24 - 2 per-CPU IPIs (meant as "self" and "other", but they are interchangeable
26 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
28 - Automatic masking on ack
29 - Default "this CPU" register view and explicit per-CPU views
31 This device also represents the FIQ interrupt sources on platforms using AIC,
41 - $ref: /schemas/interrupt-controller.yaml#
46 - enum:
47 - apple,s5l8960x-aic
48 - apple,t7000-aic
49 - apple,s8000-aic
50 - apple,t8010-aic
51 - apple,t8015-aic
52 - apple,t8103-aic
53 - const: apple,aic
55 interrupt-controller: true
57 '#interrupt-cells':
61 - 0: Hardware IRQ
62 - 1: FIQ
65 - HW IRQs: interrupt number
66 - FIQs:
67 - 0: physical HV timer
68 - 1: virtual HV timer
69 - 2: physical guest timer
70 - 3: virtual guest timer
71 - 4: 'efficient' CPU PMU
72 - 5: 'performance' CPU PMU
82 power-domains:
89 FIQ affinity can be expressed as a single "affinities" node,
90 containing a set of sub-nodes, one per FIQ with a non-default
93 "^.+-affinity$":
97 apple,fiq-index:
99 The interrupt number specified as a FIQ, and for which
110 - apple,fiq-index
111 - cpus
114 - compatible
115 - '#interrupt-cells'
116 - interrupt-controller
117 - reg
122 - |
124 #address-cells = <2>;
125 #size-cells = <2>;
127 aic: interrupt-controller@23b100000 {
128 compatible = "apple,t8103-aic", "apple,aic";
129 #interrupt-cells = <3>;
130 interrupt-controller;