drivers/irqchip/irq-bcm2835.c

1 // SPDX-License-Identifier: GPL-2.0+
29  * The FIQ control register:
30  *  Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
31  *  Bit    7: Enable FIQ generation
34  * An interrupt must be disabled before configuring it for FIQ generation
94 	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);  in armctrl_mask_irq()
99 	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);  in armctrl_unmask_irq()
103 	.name = "ARMCTRL-level",
115 		return -EINVAL;  in armctrl_xlate()
118 		return -EINVAL;  in armctrl_xlate()
121 		return -EINVAL;  in armctrl_xlate()
124 		return -EINVAL;  in armctrl_xlate()
176 		pr_err(FW_BUG "Bootloader left fiq enabled\n");  in armctrl_of_init()
210  * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
217 	return MAKE_HWIRQ(bank, ffs(stat) - 1);  in armctrl_translate_bank()
222 	return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);  in armctrl_translate_shortcut()
232 		return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);  in get_next_armctrl_hwirq()
262 IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
264 IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",