| /linux-6.12.1/Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 1 Altera SoCFPGA ECC Manager
2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
3 The ECC Manager counts and corrects single bit errors and counts/handles
6 Cyclone5 and Arria5 ECC Manager
8 - compatible : Should be "altr,socfpga-ecc-manager"
15 L2 Cache ECC
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
22 On Chip RAM ECC
24 - compatible : Should be "altr,socfpga-ocram-ecc"
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| /linux-6.12.1/drivers/mtd/nand/ |
| D | ecc-mtk.c | 3 * MTK ECC controller driver.
18 #include <linux/mtd/nand-ecc-mtk.h>
71 /* ecc strength that each IP supports */
126 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, in mtk_ecc_wait_idle() argument
129 struct device *dev = ecc->dev; in mtk_ecc_wait_idle()
133 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, in mtk_ecc_wait_idle()
143 struct mtk_ecc *ecc = id; in mtk_ecc_irq() local
146 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) in mtk_ecc_irq()
149 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); in mtk_ecc_irq()
150 if (dec & ecc->sectors) { in mtk_ecc_irq()
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| D | ecc.c | 3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
20 * controllers. In the pipeline case, the ECC bytes are
23 * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side.
28 * - prepare: Prepare an I/O request. Enable/disable the ECC engine based on
30 * engine, this step may involve to derive the ECC bytes and place
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| D | ecc-sw-bch.c | 3 * This file provides ECC correction for more than 1 bit per block of data,
15 #include <linux/mtd/nand-ecc-sw-bch.h>
18 * nand_ecc_sw_bch_calculate - Calculate the ECC corresponding to a data block
21 * @code: Output buffer with ECC
26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
30 bch_encode(engine_conf->bch, buf, nand->ecc.ctx.conf.step_size, code); in nand_ecc_sw_bch_calculate()
44 * @read_ecc: ECC bytes from the chip
45 * @calc_ecc: ECC calculated from the raw data
52 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_correct()
53 unsigned int step_size = nand->ecc.ctx.conf.step_size; in nand_ecc_sw_bch_correct()
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| /linux-6.12.1/drivers/mtd/nand/raw/ingenic/ |
| D | ingenic_ecc.c | 3 * JZ47xx ECC common code
19 * ingenic_ecc_calculate() - calculate ECC for a data buffer
20 * @ecc: ECC device.
21 * @params: ECC parameters.
23 * @ecc_code: output buffer with ECC.
25 * Return: 0 on success, -ETIMEDOUT if timed out while waiting for ECC
28 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
32 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
37 * @ecc: ECC device.
38 * @params: ECC parameters.
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| D | ingenic_nand_drv.c | 44 struct ingenic_ecc *ecc; member
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc() local
77 if (section || !ecc->total) in qi_lb60_ooblayout_ecc()
80 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc()
90 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_free() local
95 oobregion->length = mtd->oobsize - ecc->total - 12; in qi_lb60_ooblayout_free()
96 oobregion->offset = 12 + ecc->total; in qi_lb60_ooblayout_free()
102 .ecc = qi_lb60_ooblayout_ecc,
110 struct nand_ecc_ctrl *ecc = &chip->ecc; in jz4725b_ooblayout_ecc() local
112 if (section || !ecc->total) in jz4725b_ooblayout_ecc()
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| D | jz4740_ecc.c | 3 * JZ4740 ECC controller driver
45 static void jz4740_ecc_reset(struct ingenic_ecc *ecc, bool calc_ecc) in jz4740_ecc_reset() argument
50 writel(0, ecc->base + JZ_REG_NAND_IRQ_STAT); in jz4740_ecc_reset()
52 /* Initialize and enable ECC hardware */ in jz4740_ecc_reset()
53 reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
57 if (calc_ecc) /* calculate ECC from data */ in jz4740_ecc_reset()
59 else /* correct data from ECC */ in jz4740_ecc_reset()
62 writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
65 static int jz4740_ecc_calculate(struct ingenic_ecc *ecc, in jz4740_ecc_calculate() argument
73 jz4740_ecc_reset(ecc, true); in jz4740_ecc_calculate()
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| D | ingenic_ecc.h | 17 * struct ingenic_ecc_params - ECC parameters
18 * @size: data bytes per ECC step.
19 * @bytes: ECC bytes per step.
20 * @strength: number of correctable bits per ECC step.
29 int ingenic_ecc_calculate(struct ingenic_ecc *ecc,
32 int ingenic_ecc_correct(struct ingenic_ecc *ecc,
36 void ingenic_ecc_release(struct ingenic_ecc *ecc);
39 static inline int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
46 static inline int ingenic_ecc_correct(struct ingenic_ecc *ecc, in ingenic_ecc_correct() argument
53 static inline void ingenic_ecc_release(struct ingenic_ecc *ecc) in ingenic_ecc_release() argument
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| /linux-6.12.1/drivers/dma/ti/ |
| D | edma.c | 219 struct edma_cc *ecc; member
300 static inline unsigned int edma_read(struct edma_cc *ecc, int offset) in edma_read() argument
302 return (unsigned int)__raw_readl(ecc->base + offset); in edma_read()
305 static inline void edma_write(struct edma_cc *ecc, int offset, int val) in edma_write() argument
307 __raw_writel(val, ecc->base + offset); in edma_write()
310 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, in edma_modify() argument
313 unsigned val = edma_read(ecc, offset); in edma_modify()
317 edma_write(ecc, offset, val); in edma_modify()
320 static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or) in edma_or() argument
322 unsigned val = edma_read(ecc, offset); in edma_or()
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| /linux-6.12.1/drivers/mtd/nand/raw/ |
| D | nand_micron.c | 15 * corrected by on-die ECC and should be rewritten.
20 * On chips with 8-bit ECC and additional bit can be used to distinguish
66 struct micron_on_die_ecc ecc; member
127 .ecc = micron_nand_on_die_4_ooblayout_ecc,
140 oobregion->offset = mtd->oobsize - chip->ecc.total; in micron_nand_on_die_8_ooblayout_ecc()
141 oobregion->length = chip->ecc.total; in micron_nand_on_die_8_ooblayout_ecc()
156 oobregion->length = mtd->oobsize - chip->ecc.total - 2; in micron_nand_on_die_8_ooblayout_free()
162 .ecc = micron_nand_on_die_8_ooblayout_ecc,
172 if (micron->ecc.forced) in micron_nand_on_die_ecc_setup()
175 if (micron->ecc.enabled == enable) in micron_nand_on_die_ecc_setup()
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| D | omap2.c | 18 #include <linux/mtd/nand-ecc-sw-bch.h>
122 /* GPMC ecc engine settings for read */
129 /* GPMC ecc engine settings for write */
170 /* fields specific for BCHx_HW ECC scheme */
623 * gen_true_ecc - This function will generate true ECC value
624 * @ecc_buf: buffer to store ecc code
626 * This generated true ECC value can be used when correcting
644 * @ecc_data1: ecc code from nand spare area
645 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
648 * This function compares two ECC's and indicates if there is an error.
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| D | nand_base.c | 22 * if we have HW ECC support.
38 #include <linux/mtd/nand-ecc-sw-hamming.h>
39 #include <linux/mtd/nand-ecc-sw-bch.h>
262 res = chip->ecc.read_oob(chip, first_page + page_offset); in nand_block_bad()
479 status = chip->ecc.write_oob_raw(chip, page & chip->pagemask); in nand_do_write_oob()
481 status = chip->ecc.write_oob(chip, page & chip->pagemask); in nand_do_write_oob()
2841 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
2845 * @ecc: ECC buffer
2846 * @ecclen: ECC length
2851 * Check if a data buffer and its associated ECC and OOB data contains only
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| D | sunxi_nand.c | 172 * struct sunxi_nand_hw_ecc - stores information related to HW ECC support
185 * @ecc: ECC controller structure
195 struct sunxi_nand_hw_ecc ecc; member
603 bool ecc) in sunxi_nfc_randomizer_state() argument
612 if (ecc) { in sunxi_nfc_randomizer_state()
623 bool ecc) in sunxi_nfc_randomizer_config() argument
633 state = sunxi_nfc_randomizer_state(nand, page, ecc); in sunxi_nfc_randomizer_config()
670 bool ecc, int page) in sunxi_nfc_randomizer_write_buf() argument
672 sunxi_nfc_randomizer_config(nand, page, ecc); in sunxi_nfc_randomizer_write_buf()
679 int len, bool ecc, int page) in sunxi_nfc_randomizer_read_buf() argument
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| D | rockchip-nand-controller.c | 23 * 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data +
24 * 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data +
31 * 4Bytes sys data + .... + 4Bytes sys data + ECC data.
93 * struct rk_ecc_cnt_status: represent a ecc status data.
95 * @low: ECC count low bit index at register.
97 * @low_bn: ECC count low bit number.
98 * @high: ECC count high bit index at register.
113 * @ecc_strengths: ECC strengths
114 * @ecc_cfgs: ECC config values
197 return (u8 *)p + i * chip->ecc.size; in rk_nfc_buf_to_data_ptr()
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| D | fsmc_nand.c | 29 #include <linux/mtd/nand-ecc-sw-hamming.h>
172 if (section >= chip->ecc.steps) in fsmc_ecc1_ooblayout_ecc()
186 if (section >= chip->ecc.steps) in fsmc_ecc1_ooblayout_free()
191 if (section < chip->ecc.steps - 1) in fsmc_ecc1_ooblayout_free()
200 .ecc = fsmc_ecc1_ooblayout_ecc,
205 * ECC placement definitions in oobfree type format.
206 * There are 13 bytes of ecc for every 512 byte block and it has to be read
215 if (section >= chip->ecc.steps) in fsmc_ecc4_ooblayout_ecc()
218 oobregion->length = chip->ecc.bytes; in fsmc_ecc4_ooblayout_ecc()
233 if (section >= chip->ecc.steps) in fsmc_ecc4_ooblayout_free()
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| D | qcom_nandc.c | 172 * the NAND controller performs reads/writes with ECC in 516 byte chunks.
186 /* ECC modes supported by the controller */
448 * by ECC (value in pages)
450 * by ECC (value in pages)
491 * protected by ECC
495 * of a page, consisting of all data, ecc, spare
498 * by ECC
499 * @ecc_bytes_hw: ECC bytes used by controller hardware for this
506 * ecc/non-ecc mode for the current nand flash
513 * @use_ecc: request the controller to use ECC for the
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| D | lpc32xx_slc.c | 56 #define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
63 #define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
64 #define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */
108 /* ECC line party fetch macro */
113 * DMA requires storage space for the DMA local buffer and the hardware ECC
120 /* Number of bytes used for ECC stored in NAND per 256 bytes */
134 * NAND ECC Layout for small page NAND devices
167 .ecc = lpc32xx_ooblayout_ecc,
229 * DMA and CPU addresses of ECC work area and data buffer
325 * Prepares SLC for transfers with H/W ECC enabled
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| D | nand_toshiba.c | 17 /* ECC Status Read Command for BENAND */
20 /* ECC Status Mask for BENAND */
26 /* Max ECC Steps for BENAND */
40 NAND_OP_8BIT_DATA_IN(chip->ecc.steps, ecc_status, 0), in toshiba_nand_benand_read_eccstatus_op()
62 for (i = 0; i < chip->ecc.steps; i++) { in toshiba_nand_benand_eccstatus()
128 * The calculated ECC bytes are stored into other isolated in toshiba_nand_benand_init()
130 * This is why chip->ecc.bytes = 0. in toshiba_nand_benand_init()
132 chip->ecc.bytes = 0; in toshiba_nand_benand_init()
133 chip->ecc.size = 512; in toshiba_nand_benand_init()
134 chip->ecc.strength = 8; in toshiba_nand_benand_init()
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| /linux-6.12.1/Documentation/devicetree/bindings/mtd/ |
| D | nand-chip.yaml | 25 nand-ecc-engine:
27 A phandle on the hardware ECC engine if any. There are
29 1/ The ECC engine is part of the NAND controller, in this
31 2/ The ECC engine is part of the NAND part (on-die), in this
33 3/ The ECC engine is external, in this case the phandle should
34 reference the specific ECC engine node.
37 nand-use-soft-ecc-engine:
38 description: Use a software ECC engine.
41 nand-no-ecc-engine:
42 description: Do not use any ECC correction.
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| D | rockchip,nand-controller.yaml | 66 nand-ecc-mode:
69 nand-ecc-step-size:
72 nand-ecc-strength:
75 The ECC configurations that can be supported are as follows.
76 NFC v600 ECC 16, 24, 40, 60
79 NFC v622 ECC 16, 24, 40, 60
82 NFC v800 ECC 16
85 NFC v900 ECC 16, 40, 60, 70
96 The NFC driver need this information to select ECC
100 rockchip,boot-ecc-strength:
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| D | hisi504-nand.txt | 11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
20 The following ECC strength and step size are currently supported:
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
34 nand-ecc-mode = "hw";
35 nand-ecc-strength = <16>;
36 nand-ecc-step-size = <1024>;
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| D | raw-nand-chip.yaml | 16 The ECC strength and ECC step size properties define the user
18 they request the ECC engine to correct {strength} bit errors per
34 nand-ecc-placement:
36 Location of the ECC bytes. This location is unknown by default
37 but can be explicitly set to "oob", if all ECC bytes are
38 known to be stored in the OOB area, or "interleaved" if ECC
44 nand-ecc-mode:
46 Legacy ECC configuration mixing the ECC engine choice and
70 nand-ecc-maximize:
72 Whether or not the ECC strength should be maximized. The
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| D | mediatek,nand-ecc-engine.yaml | 4 $id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml#
7 title: MediaTek(MTK) SoCs NAND ECC engine
13 MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
18 - mediatek,mt2701-ecc
19 - mediatek,mt2712-ecc
20 - mediatek,mt7622-ecc
21 - mediatek,mt7986-ecc
25 - description: Base physical address and size of ECC.
29 - description: ECC interrupt
56 bch: ecc@1100e000 {
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| /linux-6.12.1/arch/arm/mach-socfpga/ |
| D | ocram.c | 21 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); in socfpga_init_ocram_ecc()
23 pr_err("Unable to find socfpga-ocram-ecc\n"); in socfpga_init_ocram_ecc()
30 pr_err("Unable to map OCRAM ecc regs.\n"); in socfpga_init_ocram_ecc()
34 /* Clear any pending OCRAM ECC interrupts, then enable ECC */ in socfpga_init_ocram_ecc()
58 /* ECC Manager Defines */
89 * This function uses the memory initialization block in the Arria10 ECC
90 * controller to initialize/clear the entire memory data and ECC data.
106 /* Clear any pending ECC interrupts */ in altr_init_memory_port()
125 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-a10-ocram-ecc"); in socfpga_init_arria10_ocram_ecc()
127 pr_err("Unable to find socfpga-a10-ocram-ecc\n"); in socfpga_init_arria10_ocram_ecc()
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| /linux-6.12.1/Documentation/driver-api/ |
| D | mtdnand.rst | 357 Hardware ECC support
363 The nand driver supports three different types of hardware ECC.
367 Hardware ECC generator providing 3 bytes ECC per 256 byte.
371 Hardware ECC generator providing 3 bytes ECC per 512 byte.
375 Hardware ECC generator providing 6 bytes ECC per 512 byte.
379 Hardware ECC generator providing 8 bytes ECC per 512 byte.
396 Transfer the ECC from the hardware to the buffer. If the option
402 In case of an ECC error this function is called for error detection
409 Hardware ECC with syndrome calculation
412 Many hardware ECC implementations provide Reed-Solomon codes and
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