29 #include <linux/mtd/nand-ecc-sw-hamming.h>
172 	if (section >= chip->ecc.steps)  in fsmc_ecc1_ooblayout_ecc()
186 	if (section >= chip->ecc.steps)  in fsmc_ecc1_ooblayout_free()
191 	if (section < chip->ecc.steps - 1)  in fsmc_ecc1_ooblayout_free()
200 	.ecc = fsmc_ecc1_ooblayout_ecc,
205  * ECC placement definitions in oobfree type format.
206  * There are 13 bytes of ecc for every 512 byte block and it has to be read
215 	if (section >= chip->ecc.steps)  in fsmc_ecc4_ooblayout_ecc()
218 	oobregion->length = chip->ecc.bytes;  in fsmc_ecc4_ooblayout_ecc()
233 	if (section >= chip->ecc.steps)  in fsmc_ecc4_ooblayout_free()
238 	if (section < chip->ecc.steps - 1)  in fsmc_ecc4_ooblayout_free()
247 	.ecc = fsmc_ecc4_ooblayout_ecc,
372  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
387  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
388  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
392 				u8 *ecc)  in fsmc_read_hwecc_ecc4()  argument
406 		dev_err(host->dev, "calculate ecc timed out\n");  in fsmc_read_hwecc_ecc4()
411 	ecc[0] = ecc_tmp;  in fsmc_read_hwecc_ecc4()
412 	ecc[1] = ecc_tmp >> 8;  in fsmc_read_hwecc_ecc4()
413 	ecc[2] = ecc_tmp >> 16;  in fsmc_read_hwecc_ecc4()
414 	ecc[3] = ecc_tmp >> 24;  in fsmc_read_hwecc_ecc4()
417 	ecc[4] = ecc_tmp;  in fsmc_read_hwecc_ecc4()
418 	ecc[5] = ecc_tmp >> 8;  in fsmc_read_hwecc_ecc4()
419 	ecc[6] = ecc_tmp >> 16;  in fsmc_read_hwecc_ecc4()
420 	ecc[7] = ecc_tmp >> 24;  in fsmc_read_hwecc_ecc4()
423 	ecc[8] = ecc_tmp;  in fsmc_read_hwecc_ecc4()
424 	ecc[9] = ecc_tmp >> 8;  in fsmc_read_hwecc_ecc4()
425 	ecc[10] = ecc_tmp >> 16;  in fsmc_read_hwecc_ecc4()
426 	ecc[11] = ecc_tmp >> 24;  in fsmc_read_hwecc_ecc4()
429 	ecc[12] = ecc_tmp >> 16;  in fsmc_read_hwecc_ecc4()
435  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
436  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
440 				u8 *ecc)  in fsmc_read_hwecc_ecc1()  argument
446 	ecc[0] = ecc_tmp;  in fsmc_read_hwecc_ecc1()
447 	ecc[1] = ecc_tmp >> 8;  in fsmc_read_hwecc_ecc1()
448 	ecc[2] = ecc_tmp >> 16;  in fsmc_read_hwecc_ecc1()
458 	bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER;  in fsmc_correct_ecc1()
461 				      chip->ecc.size, sm_order);  in fsmc_correct_ecc1()
701  * data(512 byte) -> ecc(13 byte)
709 	int i, j, s, stat, eccsize = chip->ecc.size;  in fsmc_read_page_hwecc()
710 	int eccbytes = chip->ecc.bytes;  in fsmc_read_page_hwecc()
711 	int eccsteps = chip->ecc.steps;  in fsmc_read_page_hwecc()
713 	u8 *ecc_calc = chip->ecc.calc_buf;  in fsmc_read_page_hwecc()
714 	u8 *ecc_code = chip->ecc.code_buf;  in fsmc_read_page_hwecc()
727 		chip->ecc.hwctl(chip, NAND_ECC_READ);  in fsmc_read_page_hwecc()
754 		memcpy(&ecc_code[i], oob, chip->ecc.bytes);  in fsmc_read_page_hwecc()
755 		chip->ecc.calculate(chip, p, &ecc_calc[i]);  in fsmc_read_page_hwecc()
757 		stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);  in fsmc_read_page_hwecc()
773  * @read_ecc:	ecc read from device spare area
774  * @calc_ecc:	ecc calculated from read data
797 		 * would result in an ecc error because the oob data is also  in fsmc_bch8_correct_data()
798 		 * erased to FF and the calculated ecc for an FF data is not  in fsmc_bch8_correct_data()
809 		int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);  in fsmc_bch8_correct_data()
810 		int bits_data = count_written_bits(dat, chip->ecc.size, 8);  in fsmc_bch8_correct_data()
814 				memset(dat, 0xff, chip->ecc.size);  in fsmc_bch8_correct_data()
848 		if (err_idx[i] < chip->ecc.size * 8) {  in fsmc_bch8_correct_data()
914 	if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)  in fsmc_nand_attach_chip()
915 		nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;  in fsmc_nand_attach_chip()
917 	if (!nand->ecc.size)  in fsmc_nand_attach_chip()
918 		nand->ecc.size = 512;  in fsmc_nand_attach_chip()
921 		nand->ecc.read_page = fsmc_read_page_hwecc;  in fsmc_nand_attach_chip()
922 		nand->ecc.calculate = fsmc_read_hwecc_ecc4;  in fsmc_nand_attach_chip()
923 		nand->ecc.correct = fsmc_bch8_correct_data;  in fsmc_nand_attach_chip()
924 		nand->ecc.bytes = 13;  in fsmc_nand_attach_chip()
925 		nand->ecc.strength = 8;  in fsmc_nand_attach_chip()
948 	switch (nand->ecc.engine_type) {  in fsmc_nand_attach_chip()
950 		dev_info(host->dev, "Using 1-bit HW ECC scheme\n");  in fsmc_nand_attach_chip()
951 		nand->ecc.calculate = fsmc_read_hwecc_ecc1;  in fsmc_nand_attach_chip()
952 		nand->ecc.correct = fsmc_correct_ecc1;  in fsmc_nand_attach_chip()
953 		nand->ecc.hwctl = fsmc_enable_hwecc;  in fsmc_nand_attach_chip()
954 		nand->ecc.bytes = 3;  in fsmc_nand_attach_chip()
955 		nand->ecc.strength = 1;  in fsmc_nand_attach_chip()
956 		nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;  in fsmc_nand_attach_chip()
960 		if (nand->ecc.algo == NAND_ECC_ALGO_BCH) {  in fsmc_nand_attach_chip()
962 				 "Using 4-bit SW BCH ECC scheme\n");  in fsmc_nand_attach_chip()
971 		dev_err(host->dev, "Unsupported ECC mode!\n");  in fsmc_nand_attach_chip()
976 	 * Don't set layout for BCH4 SW ECC. This will be  in fsmc_nand_attach_chip()
979 	if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {  in fsmc_nand_attach_chip()