Lines Matching full:ecc
172 * the NAND controller performs reads/writes with ECC in 516 byte chunks.
186 /* ECC modes supported by the controller */
448 * by ECC (value in pages)
450 * by ECC (value in pages)
491 * protected by ECC
495 * of a page, consisting of all data, ecc, spare
498 * by ECC
499 * @ecc_bytes_hw: ECC bytes used by controller hardware for this
506 * ecc/non-ecc mode for the current nand flash
513 * @use_ecc: request the controller to use ECC for the
515 * @bch_enabled: flag to tell whether BCH ECC mode is used
550 * @ecc_modes - ecc mode for NAND
765 static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw) in qcom_nandc_is_last_cw() argument
767 return cw == (ecc->steps - 1); in qcom_nandc_is_last_cw()
775 struct nand_ecc_ctrl *ecc = &chip->ecc; in nandc_set_read_loc() local
778 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
783 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
1240 struct nand_ecc_ctrl *ecc = &chip->ecc; in config_nand_cw_read() local
1244 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in config_nand_cw_read()
1389 * when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read
1392 * when using RS ECC, the HW reports the same erros when reading an erased CW,
1396 * verify if the page is erased or not, and fix up the page for RS ECC by
1468 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_cw_raw() local
1480 raw_cw = ecc->steps - 1; in qcom_nandc_read_cw_raw()
1487 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_read_cw_raw()
1490 if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { in qcom_nandc_read_cw_raw()
1491 data_size2 = ecc->size - data_size1 - in qcom_nandc_read_cw_raw()
1492 ((ecc->steps - 1) * 4); in qcom_nandc_read_cw_raw()
1493 oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + in qcom_nandc_read_cw_raw()
1537 * number of 0 in each CW for which ECC engine returns the uncorrectable
1539 * equal to the ecc->strength for each CW.
1547 * The BBM and spare bytes bit flip won’t affect the ECC so don’t check
1557 struct nand_ecc_ctrl *ecc = &chip->ecc; in check_for_erased_page() local
1569 for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { in check_for_erased_page()
1570 if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { in check_for_erased_page()
1571 data_size = ecc->size - ((ecc->steps - 1) * 4); in check_for_erased_page()
1572 oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; in check_for_erased_page()
1580 cw_oob_buf = oob_buf + (cw * ecc->bytes); in check_for_erased_page()
1594 0, ecc->strength); in check_for_erased_page()
1608 * errors. this is equivalent to what 'ecc->correct()' would do.
1616 struct nand_ecc_ctrl *ecc = &chip->ecc; in parse_read_errors() local
1626 for (i = 0; i < ecc->steps; i++, buf++) { in parse_read_errors()
1630 if (qcom_nandc_is_last_cw(ecc, i)) { in parse_read_errors()
1631 data_len = ecc->size - ((ecc->steps - 1) << 2); in parse_read_errors()
1632 oob_len = ecc->steps << 2; in parse_read_errors()
1643 * Check ECC failure for each codeword. ECC failure can in parse_read_errors()
1645 * 1. If number of bitflips are greater than ECC engine in parse_read_errors()
1652 * For BCH ECC, ignore erased codeword errors, if in parse_read_errors()
1658 * For RS ECC, HW reports the erased CW by placing in parse_read_errors()
1681 * No ECC or operational errors happened. Check the number of in parse_read_errors()
1695 oob_buf += oob_len + ecc->bytes; in parse_read_errors()
1710 * helper to perform the actual page read operation, used by ecc->read_page(),
1711 * ecc->read_oob()
1718 struct nand_ecc_ctrl *ecc = &chip->ecc; in read_page_ecc() local
1725 for (i = 0; i < ecc->steps; i++) { in read_page_ecc()
1728 if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { in read_page_ecc()
1729 data_size = ecc->size - ((ecc->steps - 1) << 2); in read_page_ecc()
1730 oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + in read_page_ecc()
1757 * when ecc is enabled, the controller doesn't read the real in read_page_ecc()
1759 * consistent layout across RAW and ECC reads, we just in read_page_ecc()
1796 struct nand_ecc_ctrl *ecc = &chip->ecc; in copy_last_cw() local
1807 set_address(host, host->cw_size * (ecc->steps - 1), page); in copy_last_cw()
1808 update_rw_regs(host, 1, true, ecc->steps - 1); in copy_last_cw()
1810 config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1); in copy_last_cw()
1884 /* implements ecc->read_page() */
1890 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_page() local
1902 update_rw_regs(host, ecc->steps, true, 0); in qcom_nandc_read_page()
1912 /* implements ecc->read_page_raw() */
1918 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_page_raw() local
1925 for (cw = 0; cw < ecc->steps; cw++) { in qcom_nandc_read_page_raw()
1932 oob_buf += ecc->bytes; in qcom_nandc_read_page_raw()
1938 /* implements ecc->read_oob() */
1943 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_oob() local
1953 update_rw_regs(host, ecc->steps, true, 0); in qcom_nandc_read_oob()
1958 /* implements ecc->write_page() */
1964 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_page() local
1983 update_rw_regs(host, ecc->steps, false, 0); in qcom_nandc_write_page()
1986 for (i = 0; i < ecc->steps; i++) { in qcom_nandc_write_page()
1989 if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { in qcom_nandc_write_page()
1990 data_size = ecc->size - ((ecc->steps - 1) << 2); in qcom_nandc_write_page()
1991 oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + in qcom_nandc_write_page()
1995 oob_size = ecc->bytes; in qcom_nandc_write_page()
1999 i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0); in qcom_nandc_write_page()
2002 * when ECC is enabled, we don't really need to write anything in qcom_nandc_write_page()
2004 * just contain ECC bytes that's written by the controller in qcom_nandc_write_page()
2008 if (qcom_nandc_is_last_cw(ecc, i)) { in qcom_nandc_write_page()
2030 /* implements ecc->write_page_raw() */
2038 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_page_raw() local
2053 update_rw_regs(host, ecc->steps, false, 0); in qcom_nandc_write_page_raw()
2056 for (i = 0; i < ecc->steps; i++) { in qcom_nandc_write_page_raw()
2060 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_write_page_raw()
2063 if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { in qcom_nandc_write_page_raw()
2064 data_size2 = ecc->size - data_size1 - in qcom_nandc_write_page_raw()
2065 ((ecc->steps - 1) << 2); in qcom_nandc_write_page_raw()
2066 oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + in qcom_nandc_write_page_raw()
2104 * implements ecc->write_oob()
2107 * since ECC is calculated for the combined codeword. So update the OOB from
2115 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_oob() local
2127 data_size = ecc->size - ((ecc->steps - 1) << 2); in qcom_nandc_write_oob()
2135 set_address(host, host->cw_size * (ecc->steps - 1), page); in qcom_nandc_write_oob()
2157 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_block_bad() local
2164 * the beginning of the last codeword, we don't care about reading ecc in qcom_nandc_block_bad()
2180 bbpos = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_block_bad()
2194 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_block_markbad() local
2211 set_address(host, host->cw_size * (ecc->steps - 1), page); in qcom_nandc_block_markbad()
2212 update_rw_regs(host, 1, false, ecc->steps - 1); in qcom_nandc_block_markbad()
2231 * Layout with ECC enabled:
2235 * | DATA xx..ECC..yy| | DATA **SPARE**xx..ECC..yy|
2243 * . = ECC bytes
2253 * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
2254 * the number of ECC bytes vary based on the ECC strength and the bus width.
2257 * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
2260 * When we access a page with ECC enabled, the reserved bytes(s) are not
2265 * Layout with ECC disabled:
2269 * | DATA1 yy DATA2 xx..ECC..| | DATA1 bb DATA2 **SPARE**xx..ECC..|
2277 * . = ECC bytes
2284 * when the ECC block is disabled, one reserved byte (or two for 16 bit bus
2288 * In order to have a consistent layout between RAW and ECC modes, we assume
2293 * |yyxx..ECC..| |bb*FREEOOB*xx..ECC..|
2301 * . = ECC bytes
2303 * y = Dummy bad block byte(s) (inaccessible when ECC enabled)
2305 * b = Real bad block byte(s) (inaccessible when ECC enabled)
2307 * This layout is read as is when ECC is disabled. When ECC is enabled, the
2309 * and assumed as 0xffs when we read a page/oob. The ECC, unused and
2310 * dummy/real bad block bytes are grouped as ecc bytes (i.e, ecc->bytes is
2318 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_ooblayout_ecc() local
2324 oobregion->length = (ecc->bytes * (ecc->steps - 1)) + in qcom_nand_ooblayout_ecc()
2340 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_ooblayout_free() local
2345 oobregion->length = ecc->steps * 4; in qcom_nand_ooblayout_free()
2346 oobregion->offset = ((ecc->steps - 1) * ecc->bytes) + host->bbm_size; in qcom_nand_ooblayout_free()
2352 .ecc = qcom_nand_ooblayout_ecc,
2369 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_attach_chip() local
2376 ecc->size = NANDC_STEP_SIZE; in qcom_nand_attach_chip()
2381 * Each CW has 4 available OOB bytes which will be protected with ECC in qcom_nand_attach_chip()
2382 * so remaining bytes can be used for ECC. in qcom_nand_attach_chip()
2387 dev_err(nandc->dev, "No valid ECC settings possible\n"); in qcom_nand_attach_chip()
2391 if (ecc->strength >= 8) { in qcom_nand_attach_chip()
2392 /* 8 bit ECC defaults to BCH ECC on all platforms */ in qcom_nand_attach_chip()
2407 * if the controller supports BCH for 4 bit ECC, the controller in qcom_nand_attach_chip()
2408 * uses lesser bytes for ECC. If RS is used, the ECC bytes is in qcom_nand_attach_chip()
2440 * we consider ecc->bytes as the sum of all the non-data content in a in qcom_nand_attach_chip()
2442 * all the bytes aren't used for ECC).It is always 16 bytes for 8 bit in qcom_nand_attach_chip()
2443 * ECC and 12 bytes for 4 bit ECC in qcom_nand_attach_chip()
2445 ecc->bytes = host->ecc_bytes_hw + host->spare_bytes + host->bbm_size; in qcom_nand_attach_chip()
2447 ecc->read_page = qcom_nandc_read_page; in qcom_nand_attach_chip()
2448 ecc->read_page_raw = qcom_nandc_read_page_raw; in qcom_nand_attach_chip()
2449 ecc->read_oob = qcom_nandc_read_oob; in qcom_nand_attach_chip()
2450 ecc->write_page = qcom_nandc_write_page; in qcom_nand_attach_chip()
2451 ecc->write_page_raw = qcom_nandc_write_page_raw; in qcom_nand_attach_chip()
2452 ecc->write_oob = qcom_nandc_write_oob; in qcom_nand_attach_chip()
2454 ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in qcom_nand_attach_chip()
2476 * spare data with ECC too. We protect spare data by default, so we set in qcom_nand_attach_chip()
2482 * total bytes in a step, either 528 bytes for 4 bit ECC, or 532 bytes in qcom_nand_attach_chip()
2483 * for 8 bit ECC in qcom_nand_attach_chip()
2485 host->cw_size = host->cw_data + ecc->bytes; in qcom_nand_attach_chip()
2538 host->cw_size, host->cw_data, ecc->strength, ecc->bytes, in qcom_nand_attach_chip()
2685 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_read_status_exec() local
2699 num_cw = nandc->exec_opwrite ? ecc->steps : 1; in qcom_read_status_exec()
3282 * of a page with ECC disabled. currently, the nand_base and nand_bbt in qcom_nand_host_init_and_register()
3283 * helpers don't allow us to read BB from a nand chip with ECC in qcom_nand_host_init_and_register()