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/linux-6.12.1/drivers/staging/axis-fifo/
Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
5 transferring data from a processor into the FPGA fabric. The driver creates
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
[all …]
/linux-6.12.1/drivers/clk/meson/
Ds4-pll.c1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
5 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
9 #include <linux/clk-provider.h>
13 #include "clk-mpll.h"
14 #include "clk-pll.h"
15 #include "clk-regmap.h"
16 #include "s4-pll.h"
17 #include "meson-clkc-utils.h"
18 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
25 * in the kernel phase. Write of fixed PLL-related register will cause the system to crash.
[all …]
Daxg.c1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
18 #include "clk-regmap.h"
19 #include "clk-pll.h"
20 #include "clk-mpll.h"
22 #include "meson-eeclk.h"
24 #include <dt-bindings/clock/axg-clkc.h>
29 .data = &(struct meson_clk_pll_data){
33 .width = 1,
[all …]
Dc3-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
11 #include "clk-regmap.h"
12 #include "clk-pll.h"
13 #include "meson-clkc-utils.h"
14 #include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
38 .data = &(struct clk_regmap_gate_data) {
79 .data = &(struct clk_regmap_gate_data) {
107 .data = &(struct clk_regmap_gate_data) {
135 .data = &(struct clk_regmap_gate_data) {
[all …]
Dclk-cpu-dyndiv.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
11 #include "clk-cpu-dyndiv.h"
16 return (struct meson_clk_cpu_dyndiv_data *)clk->data; in meson_clk_cpu_dyndiv_data()
23 struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk); in meson_clk_cpu_dyndiv_recalc_rate() local
26 meson_parm_read(clk->map, &data->div), in meson_clk_cpu_dyndiv_recalc_rate()
27 NULL, 0, data->div.width); in meson_clk_cpu_dyndiv_recalc_rate()
34 struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk); in meson_clk_cpu_dyndiv_determine_rate() local
36 return divider_determine_rate(hw, req, NULL, data->div.width, 0); in meson_clk_cpu_dyndiv_determine_rate()
[all …]
Dgxbb.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
14 #include "clk-regmap.h"
15 #include "clk-pll.h"
16 #include "clk-mpll.h"
17 #include "meson-eeclk.h"
18 #include "vid-pll-div.h"
20 #include <dt-bindings/clock/gxbb-clkc.h>
89 .data = &(struct meson_clk_pll_data){
93 .width = 1,
[all …]
/linux-6.12.1/drivers/staging/media/atomisp/pci/runtime/inputfifo/src/
Dinputfifo.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2010 - 2015, Intel Corporation.
48 /* The data type is used to send special cases:
55 * regular: used for all other data types (RAW, YUV422, etc)
105 unsigned int data) in inputfifo_send_data_a() argument
108 (data << HIVE_STR_TO_MIPI_DATA_A_LSB); in inputfifo_send_data_a()
115 unsigned int data) in inputfifo_send_data_b() argument
118 (data << _HIVE_STR_TO_MIPI_DATA_B_LSB); in inputfifo_send_data_b()
223 const unsigned short *data, in inputfifo_send_line2() argument
224 unsigned int width, in inputfifo_send_line2() argument
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/linux-6.12.1/drivers/video/fbdev/
Datafb.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 int dx, int height, int width);
8 int sy, int sx, int height, int width);
10 int dy, int dx, u32 width,
11 const u8 *data, u32 bgcolor, u32 fgcolor);
14 int dx, int height, int width);
16 int sy, int sx, int height, int width);
18 int dy, int dx, u32 width,
19 const u8 *data, u32 bgcolor, u32 fgcolor);
22 int dx, int height, int width);
[all …]
Dtgafb.c2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
37 #define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type)
118 return tgafb_register(&pdev->dev); in tgafb_pci_register()
123 tgafb_unregister(&pdev->dev); in tgafb_pci_unregister()
135 { "DEC ", "PMAGD-AA" },
169 * tgafb_check_var - Optional function. Validates a var passed in.
176 struct tga_par *par = (struct tga_par *)info->par; in tgafb_check_var()
178 if (!var->pixclock) in tgafb_check_var()
179 return -EINVAL; in tgafb_check_var()
181 if (par->tga_type == TGA_TYPE_8PLANE) { in tgafb_check_var()
[all …]
Datafb_iplan2p4.c2 * linux/drivers/video/iplan2p4.c -- Low level frame buffer operations for
25 int height, int width) in atafb_iplan2p4_copyarea() argument
47 /* odd->odd or even->even */ in atafb_iplan2p4_copyarea()
50 src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL); in atafb_iplan2p4_copyarea()
51 dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL); in atafb_iplan2p4_copyarea()
53 memmove32_col(dst, src, 0xff00ff, height, next_line - BPL * 2); in atafb_iplan2p4_copyarea()
56 width -= 8; in atafb_iplan2p4_copyarea()
58 w = width >> 4; in atafb_iplan2p4_copyarea()
63 l = next_line - w * 4; in atafb_iplan2p4_copyarea()
64 for (j = height; j > 0; j--) { in atafb_iplan2p4_copyarea()
[all …]
Datafb_iplan2p2.c2 * linux/drivers/video/iplan2p2.c -- Low level frame buffer operations for
25 int height, int width) in atafb_iplan2p2_copyarea() argument
47 /* odd->odd or even->even */ in atafb_iplan2p2_copyarea()
50 src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL); in atafb_iplan2p2_copyarea()
51 dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL); in atafb_iplan2p2_copyarea()
53 memmove32_col(dst, src, 0xff00ff, height, next_line - BPL * 2); in atafb_iplan2p2_copyarea()
56 width -= 8; in atafb_iplan2p2_copyarea()
58 w = width >> 4; in atafb_iplan2p2_copyarea()
63 l = next_line - w * 4; in atafb_iplan2p2_copyarea()
64 for (j = height; j > 0; j--) { in atafb_iplan2p2_copyarea()
[all …]
Dc2p_planar.c2 * Fast C2P (Chunky-to-Planar) Conversion
4 * Copyright (C) 2003-2008 Geert Uytterhoeven
21 * Perform a full C2P step on 32 8-bit pixels, stored in 8 32-bit words
23 * - 32 8-bit chunky pixels on input
24 * - permutated planar data (1 plane per 32-bit word) on output
38 * Array containing the permutation indices of the planar data after c2p
45 * Store a full block of planar data after c2p conversion
58 * Store a partial block of planar data after c2p conversion
74 * c2p_planar - Copy 8-bit chunky image data to a planar frame buffer
78 * @width: Image width (in pixels)
[all …]
/linux-6.12.1/drivers/clk/hisilicon/
Dclkdivider-hi6220.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
19 #define div_mask(width) ((1 << (width)) - 1) argument
22 * struct hi6220_clk_divider - divider clock for hi6220
24 * @hw: handle between common and hardware-specific interfaces
27 * @width: width of the divider bit field
36 u8 width; member
51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate()
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
54 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in hi6220_clkdiv_recalc_rate()
[all …]
/linux-6.12.1/drivers/staging/media/atomisp/pci/runtime/frame/src/
Dframe.c1 // SPDX-License-Identifier: GPL-2.0
33 unsigned int width,
70 unsigned int width,
76 static struct ia_css_frame *frame_create(unsigned int width,
97 return -EINVAL; in ia_css_frame_allocate_from_info()
101 ia_css_frame_allocate(frame, info->res.width, info->res.height, in ia_css_frame_allocate_from_info()
102 info->format, info->padded_width, in ia_css_frame_allocate_from_info()
103 info->raw_bit_depth); in ia_css_frame_allocate_from_info()
110 unsigned int width, in ia_css_frame_allocate() argument
118 if (!frame || width == 0 || height == 0) in ia_css_frame_allocate()
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/
Dmsm_media_info.h5 #define MSM_MEDIA_ALIGN(__sz, __align) (((__align) & ((__align) - 1)) ?\
6 ((((__sz) + (__align) - 1) / (__align)) * (__align)) :\
7 (((__sz) + (__align) - 1) & (~((__align) - 1))))
11 #define MSM_MEDIA_ROUNDUP(__sz, __r) (((__sz) + ((__r) - 1)) / (__r))
24 * <-------- Y/UV_Stride -------->
25 * <------- Width ------->
44 * . . . . . . . . . . . . . . . . --> Buffer size alignment
46 * Y_Stride : Width aligned to 128
47 * UV_Stride : Width aligned to 128
50 * Extradata: Arbitrary (software-imposed) padding
[all …]
/linux-6.12.1/drivers/video/fbdev/core/
Dbitblit.c2 * linux/drivers/video/console/bitblit.c -- BitBlitting Operation
28 int i, offset = (vc->vc_font.height < 10) ? 1 : 2; in update_attr()
29 int width = DIV_ROUND_UP(vc->vc_font.width, 8); in update_attr() local
30 unsigned int cellsize = vc->vc_font.height * width; in update_attr()
33 offset = cellsize - (offset * width); in update_attr()
47 int sx, int dy, int dx, int height, int width) in bit_bmove() argument
51 area.sx = sx * vc->vc_font.width; in bit_bmove()
52 area.sy = sy * vc->vc_font.height; in bit_bmove()
53 area.dx = dx * vc->vc_font.width; in bit_bmove()
54 area.dy = dy * vc->vc_font.height; in bit_bmove()
[all …]
Dfb_logo.c1 // SPDX-License-Identifier: GPL-2.0
9 int fb_logo_count __read_mostly = -1;
13 return n < 0 ? d >> -n : d << n; in safe_shift()
24 const unsigned char *clut = logo->clut; in fb_set_logocmap()
33 for (i = 0; i < logo->clutsize; i += n) { in fb_set_logocmap()
34 n = logo->clutsize - i; in fb_set_logocmap()
60 const unsigned char *clut = logo->clut; in fb_set_logo_truepalette()
67 redmask = mask[info->var.red.length < 8 ? info->var.red.length : 8]; in fb_set_logo_truepalette()
68 greenmask = mask[info->var.green.length < 8 ? info->var.green.length : 8]; in fb_set_logo_truepalette()
69 bluemask = mask[info->var.blue.length < 8 ? info->var.blue.length : 8]; in fb_set_logo_truepalette()
[all …]
/linux-6.12.1/drivers/gpu/drm/panel/
Dpanel-simple.c17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
27 #include <linux/media-bus-format.h>
46 * struct panel_desc - Describes a simple panel.
78 * @size.width: Width (in mm) of the active display area.
80 unsigned int width; member
94 * become ready and start receiving video data
103 * video data.
169 for (i = 0; i < panel->desc->num_timings; i++) { in panel_simple_get_timings_modes()
170 const struct display_timing *dt = &panel->desc->timings[i]; in panel_simple_get_timings_modes()
174 mode = drm_mode_create(connector->dev); in panel_simple_get_timings_modes()
[all …]
/linux-6.12.1/sound/core/
Dpcm_misc.c2 * PCM Interface - misc routines
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define SND_PCM_FORMAT_UNKNOWN (-1)
35 unsigned char width; /* bit width */ member
36 unsigned char phys; /* physical bit width */
37 signed char le; /* 0 = big-endian, 1 = little-endian, -1 = others */
38 signed char signd; /* 0 = unsigned, 1 = signed, -1 = others */
39 unsigned char silence[8]; /* silence data to fill */
52 .width = 8, .phys = 8, .le = -1, .signd = 1,
56 .width = 8, .phys = 8, .le = -1, .signd = 0,
[all …]
/linux-6.12.1/drivers/net/ethernet/microchip/vcap/
Dvcap_api.c1 // SPDX-License-Identifier: GPL-2.0+
53 itr->offset = offset; in vcap_iter_set()
54 itr->sw_width = sw_width; in vcap_iter_set()
55 itr->regs_per_sw = DIV_ROUND_UP(sw_width, 32); in vcap_iter_set()
56 itr->tg = tg; in vcap_iter_set()
62 * A typegroup table ends with an all-zero terminator. in vcap_iter_skip_tg()
64 while (itr->tg->width && itr->offset >= itr->tg->offset) { in vcap_iter_skip_tg()
65 itr->offset += itr->tg->width; in vcap_iter_skip_tg()
66 itr->tg++; /* next typegroup */ in vcap_iter_skip_tg()
75 sw_idx = itr->offset / itr->sw_width; in vcap_iter_update()
[all …]
/linux-6.12.1/drivers/clk/nuvoton/
Dclk-ma35d1-divider.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chi-Fang Li <cfli0@nuvoton.com>
7 #include <linux/clk-provider.h>
12 #include "clk-ma35d1.h"
18 u8 width; member
35 val = readl_relaxed(dclk->reg) >> dclk->shift; in ma35d1_clkdiv_recalc_rate()
36 val &= clk_div_mask(dclk->width); in ma35d1_clkdiv_recalc_rate()
38 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in ma35d1_clkdiv_recalc_rate()
39 CLK_DIVIDER_ROUND_CLOSEST, dclk->width); in ma35d1_clkdiv_recalc_rate()
46 return divider_round_rate(hw, rate, prate, dclk->table, in ma35d1_clkdiv_round_rate()
[all …]
/linux-6.12.1/drivers/mtd/maps/
Dpismo.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PISMO memory driver - http://www.pismoworld.org/
15 #include <linux/mtd/plat-ram.h>
22 u8 width; member
39 u8 width; member
52 struct i2c_client *client = to_i2c_client(pdev->dev.parent); in pismo_set_vpp()
55 pismo->vpp(pismo->vpp_data, on); in pismo_set_vpp()
58 static unsigned int pismo_width_to_bytes(unsigned int width) in pismo_width_to_bytes() argument
60 width &= 15; in pismo_width_to_bytes()
61 if (width > 2) in pismo_width_to_bytes()
[all …]
/linux-6.12.1/include/video/
Dsticore.h1 /* SPDX-License-Identifier: GPL-2.0 */
43 #define sti_onscreen_x(sti) (sti->glob_cfg->onscreen_x)
44 #define sti_onscreen_y(sti) (sti->glob_cfg->onscreen_y)
47 #define sti_font_x(sti) (PTR_STI(sti->font)->width)
48 #define sti_font_y(sti) (PTR_STI(sti->font)->height)
63 u32 cache : 1; /* map to data cache */
81 u32 *future_ptr; /* pointer to future data */
86 s16 onscreen_x; /* screen width in pixels */
88 s16 offscreen_x; /* offset width in pixels */
90 s16 total_x; /* frame buffer width in pixels */
[all …]
/linux-6.12.1/include/linux/
Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 /* parents need enable during gate/ungate, set rate and re-parent */
42 * struct clk_rate_request - Structure encoding the clk constraints that
77 * struct clk_duty - Structure encoding the duty cycle ratio of a clock
88 * struct clk_ops - Callback operations for hardware clocks; these are to
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/auxdisplay/
Dhit,hd44780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert@linux-m68k.org>
15 interface, which can be used in either 4-bit or 8-bit mode. By using a
24 data-gpios:
26 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
27 DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
29 - maxItems: 4
30 - maxItems: 8
[all …]

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