clk/meson/axg.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
18 #include "clk-regmap.h"
19 #include "clk-pll.h"
20 #include "clk-mpll.h"
22 #include "meson-eeclk.h"
24 #include <dt-bindings/clock/axg-clkc.h>
29 	.data = &(struct meson_clk_pll_data){
33 			.width   = 1,
38 			.width   = 9,
43 			.width   = 5,
48 			.width   = 12,
53 			.width   = 1,
58 			.width   = 1,
72 	.data = &(struct clk_regmap_div_data){
75 		.width = 2,
93 	.data = &(struct meson_clk_pll_data){
97 			.width   = 1,
102 			.width   = 9,
107 			.width   = 5,
112 			.width   = 1,
117 			.width   = 1,
131 	.data = &(struct clk_regmap_div_data){
134 		.width = 2,
190 	.data = &(struct meson_clk_pll_data){
194 			.width   = 1,
199 			.width   = 9,
204 			.width   = 5,
209 			.width   = 10,
214 			.width   = 1,
219 			.width   = 1,
236 	.data = &(struct clk_regmap_div_data){
239 		.width = 2,
262 	.data = &(struct meson_clk_pll_data){
266 			.width   = 1,
271 			.width   = 9,
276 			.width   = 5,
281 			.width   = 13,
286 			.width   = 1,
291 			.width   = 1,
309 	.data = &(struct clk_regmap_div_data){
312 		.width = 2,
338 	.data = &(struct clk_regmap_gate_data){
365 	.data = &(struct clk_regmap_gate_data){
384 		 * b) CCF has a clock hand-off mechanism to make the sure the
403 	.data = &(struct clk_regmap_gate_data){
429 	.data = &(struct clk_regmap_gate_data){
457 	.data = &(struct clk_regmap_gate_data){
472 	.data = &(struct clk_regmap_div_data){
475 		.width = 1,
488 	.data = &(struct meson_clk_mpll_data){
492 			.width   = 14,
497 			.width	 = 1,
502 			.width   = 9,
507 			.width	 = 1,
523 	.data = &(struct clk_regmap_gate_data){
539 	.data = &(struct meson_clk_mpll_data){
543 			.width   = 14,
548 			.width	 = 1,
553 			.width   = 9,
558 			.width	 = 1,
574 	.data = &(struct clk_regmap_gate_data){
590 	.data = &(struct meson_clk_mpll_data){
594 			.width   = 14,
599 			.width	 = 1,
604 			.width   = 9,
609 			.width	 = 1,
614 			.width	 = 1,
630 	.data = &(struct clk_regmap_gate_data){
646 	.data = &(struct meson_clk_mpll_data){
650 			.width   = 14,
655 			.width	 = 1,
660 			.width   = 9,
665 			.width	 = 1,
681 	.data = &(struct clk_regmap_gate_data){
715 	.data = &(struct meson_clk_pll_data){
719 			.width   = 1,
724 			.width   = 9,
729 			.width   = 5,
734 			.width   = 12,
739 			.width   = 1,
744 			.width   = 1,
761 	.data = &(struct clk_regmap_div_data){
764 		.width = 2,
779 	.data = &(struct clk_regmap_div_data){
782 		.width = 2,
797 	.data = &(struct clk_regmap_mux_data){
814 	.data = &(struct clk_regmap_mux_data){
831 	.data = &(struct clk_regmap_gate_data){
846 	.data = &(struct clk_regmap_gate_data){
871 	.data = &(struct clk_regmap_mux_data){
886 	.data = &(struct clk_regmap_div_data){
889 		.width = 7,
903 	.data = &(struct clk_regmap_gate_data){
934 	.data = &(struct clk_regmap_mux_data){
949 	.data = &(struct clk_regmap_div_data){
952 		.width = 7,
967 	.data = &(struct clk_regmap_gate_data){
984 	.data = &(struct clk_regmap_mux_data){
999 	.data = &(struct clk_regmap_div_data){
1002 		.width = 7,
1017 	.data = &(struct clk_regmap_gate_data){
1042 	.data = &(struct clk_regmap_mux_data){
1058 	.data = &(struct clk_regmap_div_data){
1061 		.width = 7,
1073 	.data = &(struct clk_regmap_gate_data){
1091 	.data = &(struct clk_regmap_mux_data){
1107 	.data = &(struct clk_regmap_div_data){
1110 		.width = 7,
1122 	.data = &(struct clk_regmap_gate_data){
1140 	.data = &(struct clk_regmap_mux_data){
1160 	.data = &(struct clk_regmap_mux_data){
1175 	.data = &(struct clk_regmap_div_data){
1178 		.width = 7,
1192 	.data = &(struct clk_regmap_gate_data){
1208 	.data = &(struct clk_regmap_mux_data){
1223 	.data = &(struct clk_regmap_div_data){
1226 		.width = 7,
1240 	.data = &(struct clk_regmap_gate_data){
1256 	.data = &(struct clk_regmap_mux_data){
1274 	.data = &(struct clk_regmap_gate_data){
1300 	.data = &(struct clk_regmap_mux_data){
1315 	.data = &(struct clk_regmap_mux_data){
1330 	.data = &(struct clk_regmap_gate_data){
1344 	.data = &(struct clk_regmap_gate_data){
1358 	.data = &(struct clk_regmap_div_data){
1361 		.width = 8,
1375 	.data = &(struct clk_regmap_div_data){
1378 		.width = 8,
1392 	.data = &(struct clk_regmap_gate_data){
1406 	.data = &(struct clk_regmap_gate_data){
1420 	.data = &(struct clk_regmap_gate_data){
1434 	.data = &(struct clk_regmap_gate_data){
1448 	.data = &(struct clk_regmap_gate_data){
1462 	.data = &(struct clk_regmap_gate_data){
1476 	.data = &(struct clk_regmap_gate_data){
1490 	.data = &(struct clk_regmap_gate_data){
1504 	.data = &(struct clk_regmap_gate_data){
1518 	.data = &(struct clk_regmap_gate_data){
1532 	.data = &(struct clk_regmap_gate_data){
1546 	.data = &(struct clk_regmap_gate_data){
1678 	.data = &(struct clk_regmap_mux_data){
1694 	.data = &(struct clk_regmap_gate_data){
1722 	.data = &(struct clk_regmap_mux_data){
1739 	.data = &(struct clk_regmap_div_data){
1742 		.width = 7,
1755 	.data = &(struct clk_regmap_gate_data){
1786 	.data = &(struct clk_regmap_mux_data){
1807 	.data = &(struct clk_regmap_div_data){
1810 		.width = 11,
1824 	.data = &(struct clk_regmap_gate_data){
2174 	{ .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
2182 		.name	= "axg-clkc",