clk/meson/gxbb.c

1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
14 #include "clk-regmap.h"
15 #include "clk-pll.h"
16 #include "clk-mpll.h"
17 #include "meson-eeclk.h"
18 #include "vid-pll-div.h"
20 #include <dt-bindings/clock/gxbb-clkc.h>
89 	.data = &(struct meson_clk_pll_data){
93 			.width   = 1,
98 			.width   = 9,
103 			.width   = 5,
108 			.width   = 12,
113 			.width   = 1,
118 			.width   = 1,
132 	.data = &(struct clk_regmap_div_data){
135 		.width = 2,
166 	.data = &(struct meson_clk_pll_data){
170 			.width   = 1,
175 			.width   = 9,
180 			.width   = 5,
185 			.width   = 12,
190 			.width   = 1,
195 			.width   = 1,
214 	.data = &(struct meson_clk_pll_data){
218 			.width   = 1,
223 			.width   = 9,
228 			.width   = 5,
239 			.width   = 10,
244 			.width   = 1,
249 			.width   = 1,
268 	.data = &(struct clk_regmap_div_data){
271 		.width = 2,
286 	.data = &(struct clk_regmap_div_data){
289 		.width = 2,
304 	.data = &(struct clk_regmap_div_data){
307 		.width = 2,
322 	.data = &(struct clk_regmap_div_data){
325 		.width = 2,
340 	.data = &(struct clk_regmap_div_data){
343 		.width = 2,
358 	.data = &(struct clk_regmap_div_data){
361 		.width = 2,
376 	.data = &(struct meson_clk_pll_data){
380 			.width   = 1,
385 			.width   = 9,
390 			.width   = 5,
395 			.width   = 1,
400 			.width   = 1,
414 	.data = &(struct clk_regmap_div_data){
417 		.width = 2,
438 	.data = &(struct meson_clk_pll_data){
442 			.width   = 1,
447 			.width   = 9,
452 			.width   = 5,
457 			.width   = 1,
462 			.width   = 1,
487 	.data = &(struct meson_clk_pll_data){
491 			.width   = 1,
496 			.width   = 9,
501 			.width   = 5,
506 			.width   = 10,
511 			.width   = 1,
516 			.width   = 1,
533 	.data = &(struct clk_regmap_div_data){
536 		.width = 2,
551 			.index = -1,
572 	.data = &(struct clk_regmap_gate_data){
599 	.data = &(struct clk_regmap_gate_data){
618 		 * b) CCF has a clock hand-off mechanism to make the sure the
637 	.data = &(struct clk_regmap_gate_data){
663 	.data = &(struct clk_regmap_gate_data){
689 	.data = &(struct clk_regmap_gate_data){
704 	.data = &(struct clk_regmap_div_data){
707 		.width = 1,
718 	.data = &(struct meson_clk_mpll_data){
722 			.width   = 14,
727 			.width	 = 1,
732 			.width   = 9,
747 	.data = &(struct meson_clk_mpll_data){
751 			.width   = 14,
756 			.width	 = 1,
761 			.width   = 9,
776 	.data = &(struct clk_regmap_gate_data){
791 			.index = -1,
799 	.data = &(struct meson_clk_mpll_data){
803 			.width   = 14,
808 			.width	 = 1,
813 			.width   = 9,
828 	.data = &(struct clk_regmap_gate_data){
842 	.data = &(struct meson_clk_mpll_data){
846 			.width   = 14,
851 			.width	 = 1,
856 			.width   = 9,
871 	.data = &(struct clk_regmap_gate_data){
896 	.data = &(struct clk_regmap_mux_data){
916 	.data = &(struct clk_regmap_div_data){
919 		.width = 7,
933 	.data = &(struct clk_regmap_gate_data){
949 	.data = &(struct clk_regmap_mux_data){
967 	.data = &(struct clk_regmap_div_data){
970 		.width = 8,
984 	.data = &(struct clk_regmap_gate_data){
1001  * muxed by a glitch-free switch. The CCF can manage this glitch-free
1002  * mux because it does top-to-bottom updates the each clock tree and
1018 	.data = &(struct clk_regmap_mux_data){
1039 	.data = &(struct clk_regmap_div_data){
1042 		.width = 7,
1056 	.data = &(struct clk_regmap_gate_data){
1072 	.data = &(struct clk_regmap_mux_data){
1093 	.data = &(struct clk_regmap_div_data){
1096 		.width = 7,
1110 	.data = &(struct clk_regmap_gate_data){
1131 	.data = &(struct clk_regmap_mux_data){
1146 	.data = &(struct clk_regmap_mux_data){
1166 	.data = &(struct clk_regmap_div_data) {
1169 		.width = 8,
1184 	.data = &(struct clk_regmap_gate_data){
1200 	.data = &(struct clk_regmap_mux_data){
1220 	.data = &(struct clk_regmap_div_data){
1223 		.width = 8,
1238 	.data = &(struct clk_regmap_gate_data){
1254 	.data = &(struct clk_regmap_mux_data){
1268 		 *The parent is specific to origin of the audio data. Let the
1282 	{ .name = "cts_slow_oscin", .index = -1 },
1288 	.data = &(struct clk_regmap_mux_data){
1303 	.data = &(struct clk_regmap_div_data){
1306 		.width = 14,
1320 	.data = &(struct clk_regmap_gate_data){
1351 	.data = &(struct clk_regmap_mux_data){
1366 	.data = &(struct clk_regmap_div_data){
1369 		.width = 7,
1384 	.data = &(struct clk_regmap_gate_data){
1401 	.data = &(struct clk_regmap_mux_data){
1416 	.data = &(struct clk_regmap_div_data){
1419 		.width = 7,
1434 	.data = &(struct clk_regmap_gate_data){
1451 	.data = &(struct clk_regmap_mux_data){
1466 	.data = &(struct clk_regmap_div_data){
1469 		.width = 7,
1484 	.data = &(struct clk_regmap_gate_data){
1509 	.data = &(struct clk_regmap_mux_data){
1528 	.data = &(struct clk_regmap_div_data){
1531 		.width = 7,
1543 	.data = &(struct clk_regmap_gate_data){
1557 	.data = &(struct clk_regmap_mux_data){
1576 	.data = &(struct clk_regmap_div_data){
1579 		.width = 7,
1591 	.data = &(struct clk_regmap_gate_data){
1605 	.data = &(struct clk_regmap_mux_data){
1636 	.data = &(struct clk_regmap_mux_data){
1655 	.data = &(struct clk_regmap_div_data){
1658 		.width = 7,
1672 	.data = &(struct clk_regmap_gate_data){
1688 	.data = &(struct clk_regmap_mux_data){
1707 	.data = &(struct clk_regmap_div_data){
1710 		.width = 7,
1724 	.data = &(struct clk_regmap_gate_data){
1740 	.data = &(struct clk_regmap_mux_data){
1762 	.data = &(struct clk_regmap_gate_data){
1778 	.data = &(struct meson_vid_pll_div_data){
1782 			.width   = 15,
1787 			.width   = 2,
1802 			.index = -1,
1818 	{ .name = "hdmi_pll", .index = -1 },
1822 	.data = &(struct clk_regmap_mux_data){
1841 	.data = &(struct clk_regmap_gate_data){
1867 	.data = &(struct clk_regmap_mux_data){
1887 	.data = &(struct clk_regmap_mux_data){
1907 	.data = &(struct clk_regmap_gate_data){
1921 	.data = &(struct clk_regmap_gate_data){
1935 	.data = &(struct clk_regmap_div_data){
1938 		.width = 8,
1952 	.data = &(struct clk_regmap_div_data){
1955 		.width = 8,
1969 	.data = &(struct clk_regmap_gate_data){
1983 	.data = &(struct clk_regmap_gate_data){
1997 	.data = &(struct clk_regmap_gate_data){
2011 	.data = &(struct clk_regmap_gate_data){
2025 	.data = &(struct clk_regmap_gate_data){
2039 	.data = &(struct clk_regmap_gate_data){
2053 	.data = &(struct clk_regmap_gate_data){
2067 	.data = &(struct clk_regmap_gate_data){
2081 	.data = &(struct clk_regmap_gate_data){
2095 	.data = &(struct clk_regmap_gate_data){
2109 	.data = &(struct clk_regmap_gate_data){
2123 	.data = &(struct clk_regmap_gate_data){
2255 	.data = &(struct clk_regmap_mux_data){
2271 	.data = &(struct clk_regmap_mux_data){
2287 	.data = &(struct clk_regmap_mux_data){
2318 	.data = &(struct clk_regmap_mux_data){
2340 	.data = &(struct clk_regmap_gate_data){
2356 	.data = &(struct clk_regmap_gate_data){
2372 	.data = &(struct clk_regmap_gate_data){
2388 	.data = &(struct clk_regmap_gate_data){
2413 	.data = &(struct clk_regmap_mux_data){
2429 	.data = &(struct clk_regmap_div_data){
2432 		.width = 7,
2444 	.data = &(struct clk_regmap_gate_data){
2467 	.data = &(struct clk_regmap_mux_data){
2483 	.data = &(struct clk_regmap_div_data){
2486 		.width = 7,
2501 	.data = &(struct clk_regmap_gate_data){
2517 	.data = &(struct clk_regmap_mux_data){
2533 	.data = &(struct clk_regmap_div_data){
2536 		.width = 7,
2551 	.data = &(struct clk_regmap_gate_data){
2583 	.data = &(struct clk_regmap_mux_data){
2604 	.data = &(struct clk_regmap_div_data){
2607 		.width = 11,
2621 	.data = &(struct clk_regmap_gate_data){
3557 	{ .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3558 	{ .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3566 		.name	= "gxbb-clkc",