clk/meson/s4-pll.c

1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
5  * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
9 #include <linux/clk-provider.h>
13 #include "clk-mpll.h"
14 #include "clk-pll.h"
15 #include "clk-regmap.h"
16 #include "s4-pll.h"
17 #include "meson-clkc-utils.h"
18 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
25  * in the kernel phase. Write of fixed PLL-related register will cause the system to crash.
30 	.data = &(struct meson_clk_pll_data){
34 			.width   = 1,
39 			.width   = 8,
44 			.width   = 17,
49 			.width   = 5,
54 			.width   = 1,
59 			.width   = 1,
73 	.data = &(struct clk_regmap_div_data){
76 		.width = 2,
105 	.data = &(struct clk_regmap_gate_data){
131 	.data = &(struct clk_regmap_gate_data){
157 	.data = &(struct clk_regmap_gate_data){
183 	.data = &(struct clk_regmap_gate_data){
209 	.data = &(struct clk_regmap_gate_data){
237 	.data = &(struct clk_regmap_gate_data){
269 	.data = &(struct meson_clk_pll_data){
273 			.width   = 1,
278 			.width   = 8,
283 			.width   = 5,
288 			.width   = 1,
293 			.width   = 1,
310 	.data = &(struct clk_regmap_div_data){
313 		.width = 3,
341 	.data = &(struct meson_clk_pll_data){
345 			.width   = 1,
350 			.width   = 8,
355 			.width   = 5,
360 			.width   = 1,
365 			.width   = 1,
383 	.data = &(struct clk_regmap_div_data){
386 		.width = 2,
402 	.data = &(struct meson_clk_pll_data){
406 			.width   = 1,
411 			.width   = 8,
416 			.width   = 5,
421 			.width   = 1,
426 			.width   = 1,
441 	.data = &(struct clk_regmap_div_data){
444 		.width = 4,
459 	.data = &(struct clk_regmap_div_data){
462 		.width = 2,
490 	.data = &(struct clk_regmap_mux_data){
524 	.data = &(struct meson_clk_mpll_data){
528 			.width   = 14,
533 			.width	 = 1,
538 			.width   = 9,
543 			.width	 = 1,
560 	.data = &(struct clk_regmap_gate_data){
578 	.data = &(struct meson_clk_mpll_data){
582 			.width   = 14,
587 			.width	 = 1,
592 			.width   = 9,
597 			.width	 = 1,
614 	.data = &(struct clk_regmap_gate_data){
632 	.data = &(struct meson_clk_mpll_data){
636 			.width   = 14,
641 			.width	 = 1,
646 			.width   = 9,
651 			.width	 = 1,
668 	.data = &(struct clk_regmap_gate_data){
686 	.data = &(struct meson_clk_mpll_data){
690 			.width   = 14,
695 			.width	 = 1,
700 			.width   = 9,
705 			.width	 = 1,
722 	.data = &(struct clk_regmap_gate_data){
816 	struct device *dev = &pdev->dev;  in meson_s4_pll_probe()
838 		s4_pll_clk_regmaps[i]->map = regmap;  in meson_s4_pll_probe()
858 		.compatible = "amlogic,s4-pll-clkc",
867 		.name	= "s4-pll-clkc",