| /linux-6.12.1/drivers/irqchip/ |
| D | irq-bcm6345-l1.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 * ENABLE/STATUS words are packed next to each other for each CPU:
19 * 0x1000_0028: CPU0_W0_STATUS IRQs 31-63
20 * 0x1000_002c: CPU0_W1_STATUS IRQs 0-31
23 * 0x1000_0038: CPU1_W0_STATUS IRQs 31-63
24 * 0x1000_003c: CPU1_W1_STATUS IRQs 0-31
31 * 0x1000_0030: CPU0_W0_STATUS IRQs 96-127
32 * 0x1000_0034: CPU0_W1_STATUS IRQs 64-95
33 * 0x1000_0038: CPU0_W2_STATUS IRQs 32-63
34 * 0x1000_003c: CPU0_W3_STATUS IRQs 0-31
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| D | irq-bcm7038-l1.c | 1 // SPDX-License-Identifier: GPL-2.0-only
79 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc, in reg_status() argument
82 return (0 * intc->n_words + word) * sizeof(u32); in reg_status()
85 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc, in reg_mask_status() argument
88 return (1 * intc->n_words + word) * sizeof(u32); in reg_mask_status()
91 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc, in reg_mask_set() argument
94 return (2 * intc->n_words + word) * sizeof(u32); in reg_mask_set()
97 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc, in reg_mask_clr() argument
100 return (3 * intc->n_words + word) * sizeof(u32); in reg_mask_clr()
121 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc); in bcm7038_l1_irq_handle() local
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| D | irq-bcm2836.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/cpu.h>
14 #include <linux/irqchip/irq-bcm2836.h>
23 static struct bcm2836_arm_irqchip_intc intc __read_mostly;
27 int cpu) in bcm2836_arm_irqchip_mask_per_cpu_irq() argument
29 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_mask_per_cpu_irq()
36 int cpu) in bcm2836_arm_irqchip_unmask_per_cpu_irq() argument
38 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_unmask_per_cpu_irq()
46 d->hwirq - LOCAL_IRQ_CNTPSIRQ, in bcm2836_arm_irqchip_mask_timer_irq()
53 d->hwirq - LOCAL_IRQ_CNTPSIRQ, in bcm2836_arm_irqchip_unmask_timer_irq()
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| D | irq-hip04.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * HiSilicon HiP04 INTC
5 * Copyright (C) 2002-2014 ARM Limited.
6 * Copyright (c) 2013-2014 HiSilicon Ltd.
7 * Copyright (c) 2013-2014 Linaro Ltd.
9 * Interrupt architecture for the HIP04 INTC:
14 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * associated CPU. The base address of the CPU interface is usually
18 * on the CPU it is accessed from.
20 * Note that IRQs 0-31 are special - they are local to each CPU.
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| D | irq-riscv-intc.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
12 #include <linux/cpu.h>
31 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
46 * On RISC-V systems local interrupts are masked or unmasked by writing
54 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_mask()
55 csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_mask()
57 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
62 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_unmask()
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| /linux-6.12.1/arch/arm/boot/dts/arm/ |
| D | arm-realview-pbx-a9.dts | 23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
42 cpu = <&CPU0>;
45 cpu = <&CPU1>;
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| D | arm-realview-eb.dts | 23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
26 #include "arm-realview-eb.dtsi"
30 compatible = "arm,realview-eb";
34 * This is the core tile with the CPU and GIC etc for the
35 * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache
39 * qemu-system-arm -M realview-eb
40 * Unless specified, QEMU will emulate an ARM926EJ-S core tile.
41 * Switches -cpu arm1136 or -cpu arm1176 emulates the other
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| D | arm-realview-pba8.dts | 23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
27 model = "ARM RealView Platform Baseboard for Cortex-A8";
28 compatible = "arm,realview-pba8";
32 #address-cells = <1>;
33 #size-cells = <0>;
34 enable-method = "arm,realview-smp";
36 cpu0: cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a8";
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| /linux-6.12.1/arch/riscv/boot/dts/sophgo/ |
| D | sg2042-cpus.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #address-cells = <1>;
9 #size-cells = <0>;
10 timebase-frequency = <50000000>;
12 cpu-map {
16 cpu = <&cpu0>;
19 cpu = <&cpu1>;
22 cpu = <&cpu2>;
25 cpu = <&cpu3>;
31 cpu = <&cpu4>;
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| /linux-6.12.1/arch/arc/boot/dts/ |
| D | axc001.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
7 * Device tree for AXC001 770D/EM6/AS221 CPU card
8 * Note that this file only supports the 770D CPU
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
26 #clock-cells = <0>;
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| D | axc003_idu.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 input_clk: input-clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
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| D | axc003.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
7 * Device tree for AXC003 CPU card: HS38x UP configuration
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 input_clk: input-clk {
25 #clock-cells = <0>;
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| /linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | qca,ath79-cpu-intc.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller
5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
9 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
13 source, should be 1 for intc
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
28 interrupt-controller {
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| D | riscv,cpu-intc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
22 the HLIC, which are routed via the platform-level interrupt controller
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| D | qca,ath79-misc-intc.txt | 7 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
8 "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
9 - reg: Base address and size of the controllers memory area
10 - interrupts: Interrupt specifier for the controllers interrupt.
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
23 interrupt-controller@18060010 {
24 compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
27 interrupt-parent = <&cpuintc>;
30 interrupt-controller;
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| D | brcm,bcm6345-l1-intc.txt | 1 Broadcom BCM6345-style Level 1 interrupt controller
4 directly to one of the HW INT lines on each CPU.
8 - 32, 64 or 128 incoming level IRQ lines
10 - Most onchip peripherals are wired directly to an L1 input
12 - A separate instance of the register set for each CPU, allowing individual
13 peripheral IRQs to be routed to any CPU
15 - Contains one or more enable/status word pairs per CPU
17 - No atomic set/clear operations
19 - No polarity/level/edge settings
21 - No FIFO or priority encoder logic; software is expected to read all
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| D | realtek,rtl-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 interrupt to be routed to one parent CPU (hardware) interrupt, or left
18 - Birger Koblitz <mail@birger-koblitz.de>
19 - Bert Vermeulen <bert@biot.com>
20 - John Crispin <john@phrozen.org>
25 - items:
26 - enum:
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| /linux-6.12.1/arch/mips/boot/dts/ingenic/ |
| D | jz4780.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
4 #include <dt-bindings/dma/jz4780-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 cpu0: cpu@0 {
16 device_type = "cpu";
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| D | jz4740.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
14 cpu0: cpu@0 {
15 device_type = "cpu";
16 compatible = "ingenic,xburst-mxu1.0";
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| D | jz4725b.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
14 cpu0: cpu@0 {
15 device_type = "cpu";
16 compatible = "ingenic,xburst-mxu1.0";
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| D | jz4770.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
14 cpu0: cpu@0 {
15 device_type = "cpu";
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
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| D | x1000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
4 #include <dt-bindings/dma/x1000-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 cpu0: cpu@0 {
16 device_type = "cpu";
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| /linux-6.12.1/Documentation/devicetree/bindings/cpufreq/ |
| D | brcm,stb-avs-cpu-freq.txt | 4 A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
5 references the mailbox register used to communicate with the AVS CPU[1]. The
6 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
7 the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
8 command sent to it by a driver. Interrupting the AVS CPU is mandatory for
12 so a driver can react to interrupts generated by the AVS CPU whenever a command
13 has been processed. See [2] for more information on the brcm,l2-intc node.
15 [1] The AVS CPU is an independent co-processor that runs proprietary
19 [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
22 Node brcm,avs-cpu-data-mem
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| /linux-6.12.1/arch/mips/boot/dts/realtek/ |
| D | rtl930x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
6 compatible = "realtek,rtl9302-soc";
9 #address-cells = <1>;
10 #size-cells = <0>;
12 cpu@0 {
13 device_type = "cpu";
17 clock-names = "cpu";
21 baseclk: clock-800mhz {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
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| /linux-6.12.1/arch/arc/kernel/ |
| D | intc-arcv2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 * -Called very early (start_kernel -> setup_arch -> setup_processor)
26 * -Platform Independent (must for any ARC Core)
27 * -Needed for each CPU (hence not foldable into init_IRQ)
59 * ARCv2 core intc provides multiple interrupt priorities (up to 16). in arc_init_IRQ()
60 * Typical builds though have only two levels (0-high, 1-low) in arc_init_IRQ()
67 irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */ in arc_init_IRQ()
68 pr_info("archs-intc\t: %d priority levels (default %d)%s\n", in arc_init_IRQ()
75 * are supported by CPU. in arc_init_IRQ()
76 * Also disable private-per-core IRQ lines so faulty external HW won't in arc_init_IRQ()
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