boot/dts/axc003_idu.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only
7  * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
14 	#address-cells = <2>;
15 	#size-cells = <2>;
18 		compatible = "simple-bus";
19 		#address-cells = <1>;
20 		#size-cells = <1>;
24 		input_clk: input-clk {
25 			#clock-cells = <0>;
26 			compatible = "fixed-clock";
27 			clock-frequency = <33333333>;
30 		core_clk: core-clk@80 {
31 			compatible = "snps,axs10x-arc-pll-clock";
33 			#clock-cells = <0>;
41 			assigned-clocks = <&core_clk>;
42 			assigned-clock-rates = <100000000>;
45 		core_intc: archs-intc@cpu {
46 			compatible = "snps,archs-intc";
47 			interrupt-controller;
48 			#interrupt-cells = <1>;
51 		idu_intc: idu-interrupt-controller {
52 			compatible = "snps,archs-idu-intc";
53 			interrupt-controller;
54 			interrupt-parent = <&core_intc>;
55 			#interrupt-cells = <1>;
59 		 * this GPIO block ORs all interrupts on CPU card (creg,..)
60 		 * to uplink only 1 IRQ to ARC core intc
62 		dw-apb-gpio@2000 {
63 			compatible = "snps,dw-apb-gpio";
65 			#address-cells = <1>;
66 			#size-cells = <0>;
68 			ictl_intc: gpio-controller@0 {
69 				compatible = "snps,dw-apb-gpio-port";
70 				gpio-controller;
71 				#gpio-cells = <2>;
72 				snps,nr-gpios = <30>;
74 				interrupt-controller;
75 				#interrupt-cells = <2>;
76 				interrupt-parent = <&idu_intc>;
81 		debug_uart: dw-apb-uart@5000 {
82 			compatible = "snps,dw-apb-uart";
84 			clock-frequency = <33333000>;
85 			interrupt-parent = <&ictl_intc>;
88 			reg-shift = <2>;
89 			reg-io-width = <4>;
93 			compatible = "snps,archs-pct";
94 			#interrupt-cells = <1>;
95 			interrupt-parent = <&core_intc>;
101 	 * Mark DMA peripherals connected via IOC port as dma-coherent. We do
104 	 * only AXS103 board has HW-coherent DMA peripherals)
105 	 * We don't need to mark pgu@17000 as dma-coherent because it uses
110 			dma-coherent;
114 			dma-coherent;
118 			dma-coherent;
122 			dma-coherent;
127 	 * This INTC is actually connected to DW APB GPIO
128 	 * which acts as a wire between MB INTC and CPU INTC.
129 	 * GPIO INTC is configured in platform init code
130 	 * and here we mimic direct connection from MB INTC to
131 	 * CPU INTC, thus we set "interrupts = <0 1>" instead of
134 	 * This intc actually resides on MB, but we move it here to
136 	 * this intc to cpu intc are different for axs101 and axs103
138 	mb_intc: interrupt-controller@e0012000 {
139 		#interrupt-cells = <1>;
140 		compatible = "snps,dw-apb-ictl";
142 		interrupt-controller;
143 		interrupt-parent = <&idu_intc>;
154 	reserved-memory {
155 		#address-cells = <2>;
156 		#size-cells = <2>;
159 		 * Move frame buffer out of IOC aperture (0x8z-0xaz).
162 			compatible = "shared-dma-pool";
164 			no-map;