1 // SPDX-License-Identifier: GPL-2.0-only
3  * HiSilicon HiP04 INTC
5  * Copyright (C) 2002-2014 ARM Limited.
6  * Copyright (c) 2013-2014 HiSilicon Ltd.
7  * Copyright (c) 2013-2014 Linaro Ltd.
9  * Interrupt architecture for the HIP04 INTC:
14  * o There is one CPU Interface per CPU, which sends interrupts sent
16  *   associated CPU. The base address of the CPU interface is usually
18  *   on the CPU it is accessed from.
20  * Note that IRQs 0-31 are special - they are local to each CPU.
22  * registers are banked per-cpu for these sources.
31 #include <linux/cpu.h>
42 #include <linux/irqchip/arm-gic.h>
48 #include "irq-gic-common.h"
62  * The GIC mapping of CPU interfaces does not necessarily match
63  * the logical CPU numbering.  Let's use a mapping as returned
74 	return hip04_data->dist_base;  in hip04_dist_base()
80 	return hip04_data->cpu_base;  in hip04_cpu_base()
85 	return d->hwirq;  in hip04_irq()
124 		return -EINVAL;  in hip04_irq_set_type()
129 		return -EINVAL;  in hip04_irq_set_type()
136 		pr_warn("GIC: PPI%d is secure or misconfigured\n", irq - 16);  in hip04_irq_set_type()
151 	unsigned int cpu, shift = (hip04_irq(d) % 2) * 16;  in hip04_irq_set_affinity()  local
155 		cpu = cpumask_any_and(mask_val, cpu_online_mask);  in hip04_irq_set_affinity()
157 		cpu = cpumask_first(mask_val);  in hip04_irq_set_affinity()
159 	if (cpu >= NR_HIP04_CPU_IF || cpu >= nr_cpu_ids)  in hip04_irq_set_affinity()
160 		return -EINVAL;  in hip04_irq_set_affinity()
165 	bit = hip04_cpu_map[cpu] << shift;  in hip04_irq_set_affinity()
170 	irq_data_update_effective_affinity(d, cpumask_of(cpu));  in hip04_irq_set_affinity()
177 	int cpu;  in hip04_ipi_send_mask()  local
182 	/* Convert our logical CPU mask into a physical one. */  in hip04_ipi_send_mask()
183 	for_each_cpu(cpu, mask)  in hip04_ipi_send_mask()
184 		map |= hip04_cpu_map[cpu];  in hip04_ipi_send_mask()
193 	writel_relaxed(map << 8 | d->hwirq, hip04_data.dist_base + GIC_DIST_SOFTINT);  in hip04_ipi_send_mask()
214 	.name			= "HIP04 INTC",
228 static u16 hip04_get_cpumask(struct hip04_irq_data *intc)  in hip04_get_cpumask()  argument
230 	void __iomem *base = intc->dist_base;  in hip04_get_cpumask()
241 		pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");  in hip04_get_cpumask()
246 static void __init hip04_irq_dist_init(struct hip04_irq_data *intc)  in hip04_irq_dist_init()  argument
250 	unsigned int nr_irqs = intc->nr_irqs;  in hip04_irq_dist_init()
251 	void __iomem *base = intc->dist_base;  in hip04_irq_dist_init()
256 	 * Set all global interrupts to this CPU only.  in hip04_irq_dist_init()
258 	cpumask = hip04_get_cpumask(intc);  in hip04_irq_dist_init()
268 static void hip04_irq_cpu_init(struct hip04_irq_data *intc)  in hip04_irq_cpu_init()  argument
270 	void __iomem *dist_base = intc->dist_base;  in hip04_irq_cpu_init()
271 	void __iomem *base = intc->cpu_base;  in hip04_irq_cpu_init()
272 	unsigned int cpu_mask, cpu = smp_processor_id();  in hip04_irq_cpu_init()  local
276 	 * Get what the GIC says our CPU mask is.  in hip04_irq_cpu_init()
278 	BUG_ON(cpu >= NR_HIP04_CPU_IF);  in hip04_irq_cpu_init()
279 	cpu_mask = hip04_get_cpumask(intc);  in hip04_irq_cpu_init()
280 	hip04_cpu_map[cpu] = cpu_mask;  in hip04_irq_cpu_init()
287 		if (i != cpu)  in hip04_irq_cpu_init()
309 	irq_set_chip_data(irq, d->host_data);  in hip04_irq_domain_map()
320 		return -EINVAL;  in hip04_irq_domain_xlate()
327 		return -EINVAL;  in hip04_irq_domain_xlate()
341 static int hip04_irq_starting_cpu(unsigned int cpu)  in hip04_irq_starting_cpu()  argument
358 		return -ENODEV;  in hip04_of_init()
361 	WARN(!hip04_data.dist_base, "fail to map hip04 intc dist registers\n");  in hip04_of_init()
364 	WARN(!hip04_data.cpu_base, "unable to map hip04 intc cpu registers\n");  in hip04_of_init()
367 	 * Initialize the CPU interface map to all CPUs.  in hip04_of_init()
368 	 * It will be refined as each CPU probes its ID.  in hip04_of_init()
375 	 * The HIP04 INTC only supports up to 510 interrupt sources.  in hip04_of_init()
383 	irq_base = irq_alloc_descs(-1, 0, nr_irqs, numa_node_id());  in hip04_of_init()
386 		return -EINVAL;  in hip04_of_init()
394 		return -EINVAL;  in hip04_of_init()
406 IRQCHIP_DECLARE(hip04_intc, "hisilicon,hip04-intc", hip04_of_init);