arc/kernel/intc-arcv2.c

1 // SPDX-License-Identifier: GPL-2.0-only
25  * -Called very early (start_kernel -> setup_arch -> setup_processor)
26  * -Platform Independent (must for any ARC Core)
27  * -Needed for each CPU (hence not foldable into init_IRQ)
59 	 * ARCv2 core intc provides multiple interrupt priorities (up to 16).  in arc_init_IRQ()
60 	 * Typical builds though have only two levels (0-high, 1-low)  in arc_init_IRQ()
67 	irq_prio = irq_bcr.prio;	/* Encoded as N-1 for N levels */  in arc_init_IRQ()
68 	pr_info("archs-intc\t: %d priority levels (default %d)%s\n",  in arc_init_IRQ()
75 	 * are supported by CPU.  in arc_init_IRQ()
76 	 * Also disable private-per-core IRQ lines so faulty external HW won't  in arc_init_IRQ()
84 		 * Only mask cpu private IRQs here.  in arc_init_IRQ()
86 		 * need to be unmasked at each cpu, with IPIs  in arc_init_IRQ()
101 	write_aux_reg(AUX_IRQ_SELECT, data->hwirq);  in arcv2_irq_mask()
107 	write_aux_reg(AUX_IRQ_SELECT, data->hwirq);  in arcv2_irq_unmask()
114 	write_aux_reg(AUX_IRQ_SELECT, data->hwirq);  in arcv2_irq_enable()
126 	.name           = "ARCv2 core Intc",
136 	 * core intc IRQs [16, 23]:  in arcv2_irq_map()
137 	 * Statically assigned always private-per-core (Timers, WDT, IPI, PCT)  in arcv2_irq_map()
161 init_onchip_IRQ(struct device_node *intc, struct device_node *parent)  in init_onchip_IRQ()  argument
171 		panic("DeviceTree incore intc not a root irq controller\n");  in init_onchip_IRQ()
173 	root_domain = irq_domain_add_linear(intc, nr_cpu_irqs, &arcv2_irq_ops, NULL);  in init_onchip_IRQ()
191 IRQCHIP_DECLARE(arc_intc, "snps,archs-intc", init_onchip_IRQ);