| /linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ |
| D | ti-aemif.txt | 1 * Device tree bindings for Texas instruments AEMIF controller
4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
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| D | arm,pl172.txt | 1 * Device tree bindings for ARM PL172/PL175/PL176 MultiPort Memory Controller
5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ti/ |
| D | dra7-atl.txt | 1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
16 Since the clock instances are part of a single IP this binding is used as a node
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| /linux-6.12.1/Documentation/devicetree/bindings/display/bridge/ |
| D | synopsys,dw-hdmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 This document defines device tree properties for the Synopsys DesignWare HDMI
14 TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
15 binding specification by itself but is meant to be referenced by device tree
16 bindings for the platform-specific integrations of the DWC HDMI TX.
18 When referenced from platform device tree bindings the properties defined in
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| D | snps,dw-mipi-dsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Philippe CORNU <philippe.cornu@foss.st.com>
13 This document defines device tree properties for the Synopsys DesignWare MIPI
14 DSI host controller. It doesn't constitute a device tree binding specification
15 by itself but is meant to be referenced by platform-specific device tree
18 When referenced from platform device tree bindings the properties defined in
19 this document are defined as follows. The platform device tree bindings are
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| /linux-6.12.1/Documentation/driver-api/media/ |
| D | camera-sensor.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 This document covers the in-kernel APIs only. For the best practices on
12 CSI-2, parallel and BT.656 buses
13 --------------------------------
15 Please see :ref:`transmitter-receiver`.
18 ---------------
20 Camera sensors have an internal clock tree including a PLL and a number of
21 divisors. The clock tree is generally configured by the driver based on a few
22 input parameters that are specific to the hardware: the external clock frequency
26 The reason why the clock frequencies are so important is that the clock signals
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| /linux-6.12.1/Documentation/devicetree/bindings/display/ |
| D | dsi-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dsi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 This document defines device tree properties common to DSI, Display
15 a device tree binding specification by itself but is meant to be referenced
16 by device tree bindings.
18 When referenced from panel device tree bindings the properties defined in
19 this document are defined as follows. The panel device tree bindings are
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| /linux-6.12.1/Documentation/devicetree/bindings/media/ |
| D | brcm,bcm2835-unicam.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/brcm,bcm2835-unicam.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
12 description: |-
14 CSI-2 or CCP2 data from image sensors or similar devices.
19 the firmware checks the device tree configuration during boot. If it finds
20 device tree nodes whose name starts with 'csi' then it will stop the firmware
21 accessing the block, and it can then safely be used via the device tree
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| /linux-6.12.1/drivers/clk/sunxi/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Legacy clock support for Allwinner SoCs"
10 bool "Legacy clock drivers"
13 Legacy clock drivers being used on older (A10, A13, A20,
15 Device Tree backward compatibility issues, in case one would
16 still use a Device Tree with one clock provider by
24 Legacy clock driver for the A31 PRCM clocks. Those are
31 Legacy clock driver for the sun8i family PRCM clocks.
39 Legacy clock driver for the A80 PRCM clocks. Those are
|
| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | amlogic,meson8b-clkc.txt | 1 * Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
3 The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
4 supplies clock to various controllers within the SoC.
8 - compatible: must be one of:
9 - "amlogic,meson8-clkc" for Meson8 (S802) SoCs
10 - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
11 - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
14 - clocks: list of clock phandles, one for each entry in clock-names
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| D | rockchip,rk3288-cru.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3288 Clock and Reset Unit (CRU)
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The RK3288 clock controller generates and supplies clocks to various
18 A revision of this SoC is available: rk3288w. The clock tree is a bit
19 different so another dt-compatible is available. Noticed that it is only
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| D | st,nomadik.txt | 3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 PLLs and clock gates.
10 - compatible: must be "stericsson,nomadik-src"
11 - reg: must contain the SRC register base and size
14 - disable-sxtalo: if present this will disable the SXTALO
17 - disable-mxtal: if present this will disable the MXTALO,
25 fixed frequency clock, as parent.
28 - compatible: must be "st,nomadik-pll-clock"
29 - clock-cells: must be 0
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| D | zynq-7000.txt | 1 Device Tree Clock bindings for the Zynq 7000 EPP
6 See clock_bindings.txt for more information on the generic clock bindings.
9 == Clock Controller ==
10 The clock controller is a logical abstraction of Zynq's clock tree. It reads
11 required input clock frequencies from the devicetree and acts as clock provider
12 for all clock consumers of PS clocks.
15 - #clock-cells : Must be 1
16 - compatible : "xlnx,ps7-clkc"
17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
18 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
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| D | renesas,emev2-smu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
15 This is not a clock provider, but clocks under SMU depend on it.
19 const: renesas,emev2-smu
24 '#address-cells':
27 '#size-cells':
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| D | samsung,exynosautov920-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynosautov920-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung ExynosAuto v920 SoC clock controller
10 - Sunyeal Hong <sunyeal.hong@samsung.com>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Sylwester Nawrocki <s.nawrocki@samsung.com>
16 ExynosAuto v920 clock controller is comprised of several CMU units, generating
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| D | google,gs101-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Google GS101 SoC clock controller
10 - Peter Griffin <peter.griffin@linaro.org>
13 Google GS101 clock controller is comprised of several CMU units, generating
15 tree nodes, and might depend on each other. The root clock in that clock tree
16 is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
17 clock in dts.
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| /linux-6.12.1/drivers/clk/keystone/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PLL clock driver for Keystone devices
6 * Murali Karicheri <m-karicheri2@ti.com>
9 #include <linux/clk-provider.h>
26 * struct clk_pll_data - pll data structure
28 * register of pll controller, else it is in the pll_ctrl0((bit 11-6)
64 * struct clk_pll - Main pll clock
79 struct clk_pll_data *pll_data = pll->pll_data; in clk_pllclk_recalc()
84 * get bits 0-5 of multiplier from pllctrl PLLM register in clk_pllclk_recalc()
87 if (pll_data->has_pllctrl) { in clk_pllclk_recalc()
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| /linux-6.12.1/Documentation/devicetree/bindings/fpga/ |
| D | fpga-region.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
18 - Supported Use Models
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| /linux-6.12.1/arch/arm/boot/dts/samsung/ |
| D | s5pv210-smdkc110.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S5PV210 SoC device tree source
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
10 * Board device tree source for YIC System SMDC110 board.
12 * NOTE: This file is completely based on original board file for mach-smdkc110
17 /dts-v1/;
18 #include <dt-bindings/input/input.h>
34 pmic_ap_clk: clock-0 {
35 /* Workaround for missing PMIC and its clock */
36 compatible = "fixed-clock";
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| D | s3c6410-smdk6410.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung S3C6410 based SMDK6410 board device tree source.
7 * Device tree source file for Samsung SMDK6410 board which is based on
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
31 fin_pll: oscillator-0 {
32 compatible = "fixed-clock";
33 clock-frequency = <12000000>;
34 clock-output-names = "fin_pll";
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| D | s3c6410.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S3C6410 SoC device tree source
12 * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional
27 valid-mask = <0xffffff7f>;
28 valid-wakeup-mask = <0x00200004>;
32 valid-mask = <0xffffffff>;
33 valid-wakeup-mask = <0x53020000>;
37 clocks: clock-controller@7e00f000 {
38 compatible = "samsung,s3c6410-clock";
40 #clock-cells = <1>;
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| D | s5pv210-torbreck.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S5PV210 SoC device tree source
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
10 * Board device tree source for Torbreck board.
12 * NOTE: This file is completely based on original board file for mach-torbreck
17 /dts-v1/;
18 #include <dt-bindings/input/input.h>
34 pmic_ap_clk: clock-0 {
35 /* Workaround for missing PMIC and its clock */
36 compatible = "fixed-clock";
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| /linux-6.12.1/arch/powerpc/platforms/512x/ |
| D | clock-commonclk.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * common clock driver support for the MPC512x platform
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
69 /* data required for the OF clock provider registration */
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
90 * those differences can get folded into this clock provider support
292 val &= (1 << len) - 1; in get_bit_field()
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
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| /linux-6.12.1/drivers/clk/imx/ |
| D | clk-composite-7ulp.c | 1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/clk-provider.h>
14 #include "../clk-fractional-divider.h"
39 spin_lock_irqsave(gate->lock, flags); in pcc_gate_enable()
42 * with this pcc clock. in pcc_gate_enable()
44 val = readl(gate->reg); in pcc_gate_enable()
46 writel(val, gate->reg); in pcc_gate_enable()
48 spin_unlock_irqrestore(gate->lock, flags); in pcc_gate_enable()
91 return ERR_PTR(-ENOMEM); in imx_ulp_clk_hw_composite()
92 mux_hw = &mux->hw; in imx_ulp_clk_hw_composite()
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| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | snps,dwc-qos-ethernet.txt | 13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
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