bindings/net/snps%2Cdwc-qos-ethernet.txt

13 - compatible: One of:
14   - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15     Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16   - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18   - "snps,dwc-qos-ethernet-4.10"
20     "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24   same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
27   - "tx"
28     The EQOS transmit path clock. The HW signal name is clk_tx_i.
29     In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
32   - "rx"
33     The EQOS receive path clock. The HW signal name is clk_rx_i.
34     In some configurations (e.g. GMII/RGMII), this clock is derived from the
35     PHY's RX clock output. In other configurations, other clocks (such as
37     In cases where the PHY clock is directly fed into the EQOS receive path
38     without intervening logic, the DT need not represent this clock, since it
41     SW-controlled clock gate, this clock should be represented in DT.
42   - "slave_bus"
43     The CPU/slave-bus (CSR) interface clock. This applies to any bus type;
46   - "master_bus"
47     The master bus interface clock. Only required in configurations that use a
48     separate clock for the master and slave bus interfaces. The HW signal name
50   - "ptp_ref"
51     The PTP reference clock. The HW signal name is clk_ptp_ref_i.
52   - "phy_ref_clk"
53     This clock is deprecated and should not be used by new compatible values.
55   - "apb_pclk"
56     This clock is deprecated and should not be used by new compatible values.
64   extend the binding with a separate clock-names entry for each of those RX
65   clocks, rather than repurposing the existing "rx" clock-names entry as a
66   generic/logical clock in a similar fashion to "master_bus" and "slave_bus".
72   - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
73     - "slave_bus"
74     - "master_bus"
75     - "rx"
76     - "tx"
77     - "ptp_ref"
78   - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
79     - "slave_bus"
80     - "master_bus"
81     - "tx"
82     - "ptp_ref"
83   - "snps,dwc-qos-ethernet-4.10" (deprecated):
84     - "phy_ref_clk"
85     - "apb_clk"
86 - interrupts: Should contain the core's combined interrupt signal
87 - phy-mode: See ethernet.txt file in the same directory
88 - resets: Phandle and reset specifiers for each entry in reset-names, in the
90 - reset-names: May contain any/all of the following depending on the IP
92   - "eqos". The reset to the entire module. The HW signal name is hreset_n
97   - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
98     - "eqos".
99   - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
100     - None.
101   - "snps,dwc-qos-ethernet-4.10" (deprecated):
102     - None.
105 - dma-coherent: Present if dma operations are coherent
106 - phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY.
108 - snps,en-lpi: If present it enables use of the AXI low-power interface
109 - snps,write-requests: Number of write requests that the AXI port can issue.
111 - snps,read-requests: Number of read requests that the AXI port can issue.
113 - snps,burst-map: Bitmap of allowed AXI burst lengths, with the LSB
115 - snps,txpbl: DMA Programmable burst length for the TX DMA
116 - snps,rxpbl: DMA Programmable burst length for the RX DMA
117 - snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during
118   TX low-power mode.
119 - phy-handle: See ethernet.txt file in the same directory
120 - mdio device tree subnode: When the GMAC has a phy connected to its local
121     mdio, there must be device tree subnode with the following
123     - compatible: Must be "snps,dwc-qos-ethernet-mdio".
124     - #address-cells: Must be <1>.
125     - #size-cells: Must be <0>.
130     - reg: phy id used to communicate to phy.
131     - device_type: Must be "ethernet-phy".
132     - fixed-mode device tree subnode: see fixed-link.txt in the same directory
139 	clock-names = "phy_ref_clk", "apb_pclk";
141 	compatible = "snps,dwc-qos-ethernet-4.10";
142 	interrupt-parent = <&intc>;
145 	phy-handle = <&phy2>;
146 	phy-mode = "gmii";
147 	phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>;
149 	snps,en-tx-lpi-clockgating;
150 	snps,en-lpi;
151 	snps,write-requests = <2>;
152 	snps,read-requests = <16>;
153 	snps,burst-map = <0x7>;
157 	dma-coherent;
160 		#address-cells = <0x1>;
161 		#size-cells = <0x0>;
163 			compatible = "ethernet-phy-ieee802.3-c22";
164 			device_type = "ethernet-phy";