1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/clk-provider.h>
14 #include "../clk-fractional-divider.h"
39 	spin_lock_irqsave(gate->lock, flags);  in pcc_gate_enable()
42 	 * with this pcc clock.  in pcc_gate_enable()
44 	val = readl(gate->reg);  in pcc_gate_enable()
46 	writel(val, gate->reg);  in pcc_gate_enable()
48 	spin_unlock_irqrestore(gate->lock, flags);  in pcc_gate_enable()
91 			return ERR_PTR(-ENOMEM);  in imx_ulp_clk_hw_composite()
92 		mux_hw = &mux->hw;  in imx_ulp_clk_hw_composite()
93 		mux->reg = reg;  in imx_ulp_clk_hw_composite()
94 		mux->shift = PCG_PCS_SHIFT;  in imx_ulp_clk_hw_composite()
95 		mux->mask = PCG_PCS_MASK;  in imx_ulp_clk_hw_composite()
97 			mux->lock = &imx_ccm_lock;  in imx_ulp_clk_hw_composite()
104 			return ERR_PTR(-ENOMEM);  in imx_ulp_clk_hw_composite()
106 		fd_hw = &fd->hw;  in imx_ulp_clk_hw_composite()
107 		fd->reg = reg;  in imx_ulp_clk_hw_composite()
108 		fd->mshift = PCG_FRAC_SHIFT;  in imx_ulp_clk_hw_composite()
109 		fd->mwidth = PCG_FRAC_WIDTH;  in imx_ulp_clk_hw_composite()
110 		fd->nshift = PCG_PCD_SHIFT;  in imx_ulp_clk_hw_composite()
111 		fd->nwidth = PCG_PCD_WIDTH;  in imx_ulp_clk_hw_composite()
112 		fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;  in imx_ulp_clk_hw_composite()
114 			fd->lock = &imx_ccm_lock;  in imx_ulp_clk_hw_composite()
122 			return ERR_PTR(-ENOMEM);  in imx_ulp_clk_hw_composite()
124 		gate_hw = &gate->hw;  in imx_ulp_clk_hw_composite()
125 		gate->reg = reg;  in imx_ulp_clk_hw_composite()
126 		gate->bit_idx = PCG_CGC_SHIFT;  in imx_ulp_clk_hw_composite()
128 			gate->lock = &imx_ccm_lock;  in imx_ulp_clk_hw_composite()
130 		 * make sure clock is gated during clock tree initialization,  in imx_ulp_clk_hw_composite()
131 		 * the HW ONLY allow clock parent/rate changed with clock gated,  in imx_ulp_clk_hw_composite()
132 		 * during clock tree initialization, clocks could be enabled  in imx_ulp_clk_hw_composite()
133 		 * by bootloader, so the HW status will mismatch with clock tree  in imx_ulp_clk_hw_composite()
134 		 * prepare count, then clock core driver will allow parent/rate  in imx_ulp_clk_hw_composite()
136 		 * prevent the parent/rate change due to the clock is enabled.  in imx_ulp_clk_hw_composite()