bindings/clock/google%2Cgs101-clock.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Google GS101 SoC clock controller
10   - Peter Griffin <peter.griffin@linaro.org>
13   Google GS101 clock controller is comprised of several CMU units, generating
15   tree nodes, and might depend on each other. The root clock in that clock tree
16   is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
17   clock in dts.
19   CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
22   Each clock is assigned an identifier and client nodes can use this identifier
23   to specify the clock which they consume. All clocks available for usage
24   in clock consumer nodes are defined as preprocessor macros in
25   'dt-bindings/clock/gs101.h' header.
30       - google,gs101-cmu-top
31       - google,gs101-cmu-apm
32       - google,gs101-cmu-misc
33       - google,gs101-cmu-hsi0
34       - google,gs101-cmu-hsi2
35       - google,gs101-cmu-peric0
36       - google,gs101-cmu-peric1
42   clock-names:
46   "#clock-cells":
53   - compatible
54   - "#clock-cells"
55   - clocks
56   - clock-names
57   - reg
60   - if:
65               - google,gs101-cmu-top
66               - google,gs101-cmu-apm
71             - description: External reference clock (24.576 MHz)
73         clock-names:
75             - const: oscclk
77   - if:
81             const: google,gs101-cmu-hsi0
87             - description: External reference clock (24.576 MHz)
88             - description: HSI0 bus clock (from CMU_TOP)
89             - description: DPGTC (from CMU_TOP)
90             - description: USB DRD controller clock (from CMU_TOP)
91             - description: USB Display Port debug clock (from CMU_TOP)
93         clock-names:
95             - const: oscclk
96             - const: bus
97             - const: dpgtc
98             - const: usb31drd
99             - const: usbdpdbg
101   - if:
106               - google,gs101-cmu-hsi2
112             - description: External reference clock (24.576 MHz)
113             - description: High Speed Interface bus clock (from CMU_TOP)
114             - description: High Speed Interface pcie clock (from CMU_TOP)
115             - description: High Speed Interface ufs clock (from CMU_TOP)
116             - description: High Speed Interface mmc clock (from CMU_TOP)
118         clock-names:
120             - const: oscclk
121             - const: bus
122             - const: pcie
123             - const: ufs
124             - const: mmc
126   - if:
130             const: google,gs101-cmu-misc
136             - description: Misc bus clock (from CMU_TOP)
137             - description: Misc sss clock (from CMU_TOP)
139         clock-names:
141             - const: bus
142             - const: sss
144   - if:
149               - google,gs101-cmu-peric0
150               - google,gs101-cmu-peric1
156             - description: External reference clock (24.576 MHz)
157             - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
158             - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
160         clock-names:
162             - const: oscclk
163             - const: bus
164             - const: ip
169   # Clock controller node for CMU_TOP
170   - |
171     #include <dt-bindings/clock/google,gs101.h>
173     cmu_top: clock-controller@1e080000 {
174         compatible = "google,gs101-cmu-top";
176         #clock-cells = <1>;
178         clock-names = "oscclk";