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/linux-6.12.1/drivers/cpufreq/
Ds3c64xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/clk.h>
58 old_freq = clk_get_rate(policy->clk) / 1000; in s3c64xx_cpufreq_set_target()
59 new_freq = s3c64xx_freq_table[index].frequency; in s3c64xx_cpufreq_set_target()
65 dvfs->vddarm_min, in s3c64xx_cpufreq_set_target()
66 dvfs->vddarm_max); in s3c64xx_cpufreq_set_target()
75 ret = clk_set_rate(policy->clk, new_freq * 1000); in s3c64xx_cpufreq_set_target()
85 dvfs->vddarm_min, in s3c64xx_cpufreq_set_target()
86 dvfs->vddarm_max); in s3c64xx_cpufreq_set_target()
90 if (clk_set_rate(policy->clk, old_freq * 1000) < 0) in s3c64xx_cpufreq_set_target()
[all …]
Dvexpress-spc-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2019 ARM Ltd.
14 #include <linux/clk.h>
48 static struct clk *clk[MAX_CLUSTERS]; variable
53 static unsigned int clk_little_max; /* Maximum clock frequency (Little) */
90 u32 rate = clk_get_rate(clk[cur_cluster]) / 1000; in clk_get_cpu_rate()
127 ret = clk_set_rate(clk[new_cluster], new_rate * 1000); in ve_spc_cpufreq_set_rate()
133 * current design of the clk core layer. To work around this in ve_spc_cpufreq_set_rate()
135 * correct. This needs to be removed once clk core is fixed. in ve_spc_cpufreq_set_rate()
137 if (clk_get_rate(clk[new_cluster]) != new_rate * 1000) in ve_spc_cpufreq_set_rate()
[all …]
Darmada-37xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
3 * CPU frequency scaling support for Armada 37xx platform.
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 #include <linux/clk.h>
24 #include "cpufreq-dt.h"
26 /* Clk register set */
124 pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000); in armada_37xx_cpu_freq_info_get()
166 * Set cpu divider based on the pre-computed array in in armada37xx_cpufreq_dvfs_setup()
186 * Find out the armada 37x supported AVS value whose voltage value is
187 * the round-up closest to the target voltage value.
[all …]
Dqcom-cpufreq-hw.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
50 * Mutex to synchronize between de-init sequence and re-starting LMh
80 dev = get_cpu_device(policy->cpu); in qcom_cpufreq_set_bw()
82 return -ENODEV; in qcom_cpufreq_set_bw()
116 struct qcom_cpufreq_data *data = policy->driver_data; in qcom_cpufreq_hw_target_index()
118 unsigned long freq = policy->freq_table[index].frequency; in qcom_cpufreq_hw_target_index()
121 writel_relaxed(index, data->base + soc_data->reg_perf_state); in qcom_cpufreq_hw_target_index()
123 if (data->per_core_dcvs) in qcom_cpufreq_hw_target_index()
124 for (i = 1; i < cpumask_weight(policy->related_cpus); i++) in qcom_cpufreq_hw_target_index()
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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
22 description: Clock output frequency in Hertz.
26 qca,clk-out-strength:
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Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
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/linux-6.12.1/arch/arm/kernel/
Dsmp_twd.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
28 static struct clk *twd_clk;
37 static int twd_shutdown(struct clock_event_device *clk) in twd_shutdown() argument
43 static int twd_set_oneshot(struct clock_event_device *clk) in twd_set_oneshot() argument
51 static int twd_set_periodic(struct clock_event_device *clk) in twd_set_periodic() argument
94 struct clock_event_device *clk = raw_cpu_ptr(twd_evt); in twd_timer_stop() local
96 twd_shutdown(clk); in twd_timer_stop()
97 disable_percpu_irq(clk->irq); in twd_timer_stop()
101 * Updates clockevent frequency when the cpu frequency changes.
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/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgm20b.c19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 #include <subdev/clk.h>
89 #define DFS_DET_RANGE 6 /* -2^6 ... 2^6-1 */
90 #define SDM_DIN_RANGE 12 /* -2^12 ... 2^12-1 */
99 .coeff_slope = -165230,
136 /* safe frequency we can use at minimum voltage */
160 gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll) in gm20b_pllg_read_mnp() argument
162 struct nvkm_subdev *subdev = &clk->base.base.subdev; in gm20b_pllg_read_mnp()
163 struct nvkm_device *device = subdev->device; in gm20b_pllg_read_mnp()
166 gk20a_pllg_read_mnp(&clk->base, &pll->base); in gm20b_pllg_read_mnp()
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/linux-6.12.1/drivers/sh/clk/
Dcore.c4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
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/linux-6.12.1/drivers/net/mdio/
Dmdio-mscc-miim.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <linux/clk.h>
14 #include <linux/mdio/mdio-mscc-miim.h>
59 struct clk *clk; member
63 /* When high resolution timers aren't built-in: we can't use usleep_range() as
76 struct mscc_miim_dev *miim = bus->priv; in mscc_miim_status()
79 ret = regmap_read(miim->regs, in mscc_miim_status()
80 MSCC_MIIM_REG_STATUS + miim->mii_status_offset, &val); in mscc_miim_status()
109 struct mscc_miim_dev *miim = bus->priv; in mscc_miim_read()
115 goto out; in mscc_miim_read()
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Dmdio-bcm-unimac.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2014-2017 Broadcom
8 #include <linux/clk.h>
17 #include <linux/platform_data/mdio-bcm-unimac.h>
43 struct clk *clk; member
50 * peripheral registers for CPU-native byte order. in unimac_mdio_readl()
53 return __raw_readl(priv->base + offset); in unimac_mdio_readl()
55 return readl_relaxed(priv->base + offset); in unimac_mdio_readl()
62 __raw_writel(val, priv->base + offset); in unimac_mdio_writel()
64 writel_relaxed(val, priv->base + offset); in unimac_mdio_writel()
[all …]
/linux-6.12.1/drivers/clocksource/
Dmps2-timer.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
51 writel_relaxed(val, to_mps2_clkevt(c)->reg + offset); in clockevent_mps2_writel()
72 u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick; in mps2_timer_set_periodic()
84 u32 status = readl_relaxed(ce->reg + TIMER_INT); in mps2_timer_interrupt()
91 writel_relaxed(1, ce->reg + TIMER_INT); in mps2_timer_interrupt()
93 ce->clkevt.event_handler(&ce->clkevt); in mps2_timer_interrupt()
101 struct clk *clk = NULL; in mps2_clockevent_init() local
105 const char *name = "mps2-clkevt"; in mps2_clockevent_init()
107 ret = of_property_read_u32(np, "clock-frequency", &rate); in mps2_clockevent_init()
[all …]
Darm_arch_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include <linux/arm-smccc.h>
77 [ARCH_TIMER_PHYS_SECURE_PPI] = "sec-phys",
80 [ARCH_TIMER_HYP_PPI] = "hyp-phys",
81 [ARCH_TIMER_HYP_VIRT_PPI] = "hyp-virt",
109 * 2) a roll-over time of not less than 40 years
118 return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64); in arch_counter_get_width()
127 struct clock_event_device *clk) in arch_timer_reg_write() argument
130 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_write()
133 writel_relaxed((u32)val, timer->base + CNTP_CTL); in arch_timer_reg_write()
[all …]
/linux-6.12.1/drivers/i2c/busses/
Di2c-digicolor.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
50 struct clk *clk; member
51 unsigned int frequency; member
73 writeb_relaxed(cmd | II_COMMAND_GO, i2c->regs + II_COMMAND); in dc_i2c_cmd()
78 u8 addr = (msg->addr & 0x7f) << 1; in dc_i2c_addr_cmd()
80 if (msg->flags & I2C_M_RD) in dc_i2c_addr_cmd()
88 writeb_relaxed(data, i2c->regs + II_DATA); in dc_i2c_data()
99 dc_i2c_write_byte(i2c, i2c->msg->buf[i2c->msgbuf_ptr++]); in dc_i2c_write_buf()
104 bool last = (i2c->msgbuf_ptr + 1 == i2c->msg->len); in dc_i2c_next_read()
[all …]
Di2c-s3c2410.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
22 #include <linux/clk.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
112 struct clk *clk; member
125 .name = "s3c2410-i2c",
128 .name = "s3c2440-i2c",
131 .name = "s3c2440-hdmiphy-i2c",
141 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
142 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
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/linux-6.12.1/drivers/pwm/
Dpwm-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/clk.h>
41 * Maximum control word value allowed when variable-frequency PWM is used as a
42 * clock for the constant-frequency PMW.
56 struct clk *clk; member
63 return __raw_readl(p->base + offset); in brcmstb_pwm_readl()
65 return readl_relaxed(p->base + offset); in brcmstb_pwm_readl()
72 __raw_writel(value, p->base + offset); in brcmstb_pwm_writel()
74 writel_relaxed(value, p->base + offset); in brcmstb_pwm_writel()
83 * Fv is derived from the variable frequency output. The variable frequency
[all …]
/linux-6.12.1/sound/soc/sh/rcar/
Dadg.c1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
6 #include <linux/clk-provider.h>
33 struct clk *clkin[CLKINMAX];
34 struct clk *clkout[CLKOUTMAX];
35 struct clk *null_clk;
50 (i < adg->clkin_size) && \
51 ((pos) = adg->clkin[i]); \
55 (i < adg->clkout_size) && \
56 ((pos) = adg->clkout[i]); \
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr_smu_msg.c19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 CTX->logger
68 } while (max_retries--); in dcn30_smu_wait_for_response()
72 TRACE_SMU_DELAY(delay_us * (initial_max_retries - max_retries), clk_mgr->base.ctx); in dcn30_smu_wait_for_response()
92 TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx); in dcn30_smu_send_msg_with_param()
211 /* Returns the actual frequency that was set in MHz, 0 on failure */
212 unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_… in dcn30_smu_set_hard_min_by_freq() argument
216 /* bits 23:16 for clock type, lower 16 bits for frequency in MHz */ in dcn30_smu_set_hard_min_by_freq()
217 uint32_t param = (clk << 16) | freq_mhz; in dcn30_smu_set_hard_min_by_freq()
219 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); in dcn30_smu_set_hard_min_by_freq()
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/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8mm-evk.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 #include <dt-bindings/usb/pd.h>
14 stdout-path = &uart2;
22 hdmi-connector {
23 compatible = "hdmi-connector";
29 remote-endpoint = <&adv7535_out>;
35 compatible = "gpio-leds";
36 pinctrl-names = "default";
[all …]
Dimx8mn-evk.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/usb/pd.h>
11 stdout-path = &uart2;
14 gpio-leds {
15 compatible = "gpio-leds";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_led>;
22 default-state = "on";
26 hdmi-connector {
27 compatible = "hdmi-connector";
[all …]
/linux-6.12.1/drivers/clk/ti/
Ddpll44xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP4-specific DPLL control functions
11 #include <linux/clk.h>
14 #include <linux/clk/ti.h>
19 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
20 * can supported when using the DPLL low-power mode. Frequencies are
22 * Status, and Low-Power Operation Mode".
37 static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) in omap4_dpllmx_allow_gatectrl() argument
42 if (!clk) in omap4_dpllmx_allow_gatectrl()
45 mask = clk->flags & CLOCK_CLKOUTX2 ? in omap4_dpllmx_allow_gatectrl()
[all …]
/linux-6.12.1/drivers/clk/sunxi-ng/
Dccu_mux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
24 if (!((common->features & CCU_FEATURE_FIXED_PREDIV) || in ccu_mux_get_prediv()
25 (common->features & CCU_FEATURE_VARIABLE_PREDIV) || in ccu_mux_get_prediv()
26 (common->features & CCU_FEATURE_ALL_PREDIV))) in ccu_mux_get_prediv()
29 if (common->features & CCU_FEATURE_ALL_PREDIV) in ccu_mux_get_prediv()
30 return common->prediv; in ccu_mux_get_prediv()
32 reg = readl(common->base + common->reg); in ccu_mux_get_prediv()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
Ddcn32_clk_mgr_smu_msg.c19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
64 } while (max_retries--); in dcn32_smu_wait_for_response()
66 TRACE_SMU_DELAY(delay_us * (initial_max_retries - max_retries), clk_mgr->base.ctx); in dcn32_smu_wait_for_response()
85 TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx); in dcn32_smu_send_msg_with_param()
100 * delay when requesting hardmin clk
121 } while (max_retries--); in dcn32_smu_wait_for_response_delay()
123 TRACE_SMU_DELAY(*total_delay_us, clk_mgr->base.ctx); in dcn32_smu_wait_for_response_delay()
145 TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx); in dcn32_smu_send_msg_with_param_delay()
162 smu_print("FCLK P-state support value is : %d\n", enable); in dcn32_smu_send_fclk_pstate_message()
195 if (ASICREV_IS_GC_11_0_0(clk_mgr->base.ctx->asic_id.hw_internal_rev)) { in dcn32_get_hard_min_status_supported()
[all …]
/linux-6.12.1/drivers/clk/pxa/
Dclk-pxa25x.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
9 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
12 #include <linux/clk-provider.h>
13 #include <linux/clk.h>
14 #include <linux/clk/pxa.h>
21 #include <dt-bindings/clock/pxa-clock.h>
22 #include "clk-pxa.h"
23 #include "clk-pxa2xx.h"
46 /* Crystal Frequency to Memory Frequency Multiplier (L) */
[all …]
/linux-6.12.1/drivers/clk/
Dclk-max9485.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk.h>
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/maxim,max9485.h>
35 unsigned long out; member
40 * Ordered by frequency. For frequency the hardware can generate with
78 struct clk *xclk;
96 drvdata->reg_value &= ~mask; in max9485_update_bits()
97 drvdata->reg_value |= value; in max9485_update_bits()
99 dev_dbg(&drvdata->client->dev, in max9485_update_bits()
[all …]

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