Lines Matching +full:clk +full:- +full:out +full:- +full:frequency
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <linux/clk.h>
14 #include <linux/mdio/mdio-mscc-miim.h>
59 struct clk *clk; member
63 /* When high resolution timers aren't built-in: we can't use usleep_range() as
76 struct mscc_miim_dev *miim = bus->priv; in mscc_miim_status()
79 ret = regmap_read(miim->regs, in mscc_miim_status()
80 MSCC_MIIM_REG_STATUS + miim->mii_status_offset, &val); in mscc_miim_status()
109 struct mscc_miim_dev *miim = bus->priv; in mscc_miim_read()
115 goto out; in mscc_miim_read()
117 ret = regmap_write(miim->regs, in mscc_miim_read()
118 MSCC_MIIM_REG_CMD + miim->mii_status_offset, in mscc_miim_read()
126 goto out; in mscc_miim_read()
131 goto out; in mscc_miim_read()
133 ret = regmap_read(miim->regs, in mscc_miim_read()
134 MSCC_MIIM_REG_DATA + miim->mii_status_offset, &val); in mscc_miim_read()
137 goto out; in mscc_miim_read()
140 if (!miim->ignore_read_errors && !!(val & MSCC_MIIM_DATA_ERROR)) { in mscc_miim_read()
141 ret = -EIO; in mscc_miim_read()
142 goto out; in mscc_miim_read()
146 out: in mscc_miim_read()
153 struct mscc_miim_dev *miim = bus->priv; in mscc_miim_write()
158 goto out; in mscc_miim_write()
160 ret = regmap_write(miim->regs, in mscc_miim_write()
161 MSCC_MIIM_REG_CMD + miim->mii_status_offset, in mscc_miim_write()
170 out: in mscc_miim_write()
176 struct mscc_miim_dev *miim = bus->priv; in mscc_miim_reset()
180 if (!miim->phy_regs) in mscc_miim_reset()
183 offset = miim->info->phy_reset_offset; in mscc_miim_reset()
184 bits = miim->info->phy_reset_bits; in mscc_miim_reset()
186 ret = regmap_update_bits(miim->phy_regs, offset, bits, 0); in mscc_miim_reset()
192 ret = regmap_update_bits(miim->phy_regs, offset, bits, bits); in mscc_miim_reset()
225 return -ENOMEM; in mscc_miim_setup()
227 bus->name = name; in mscc_miim_setup()
228 bus->read = mscc_miim_read; in mscc_miim_setup()
229 bus->write = mscc_miim_write; in mscc_miim_setup()
230 bus->reset = mscc_miim_reset; in mscc_miim_setup()
231 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(dev)); in mscc_miim_setup()
232 bus->parent = dev; in mscc_miim_setup()
234 miim = bus->priv; in mscc_miim_setup()
238 miim->regs = mii_regmap; in mscc_miim_setup()
239 miim->mii_status_offset = status_offset; in mscc_miim_setup()
240 miim->ignore_read_errors = ignore_read_errors; in mscc_miim_setup()
250 struct mscc_miim_dev *miim = bus->priv; in mscc_miim_clk_set()
255 if (!miim->bus_freq) in mscc_miim_clk_set()
258 rate = clk_get_rate(miim->clk); in mscc_miim_clk_set()
260 div = DIV_ROUND_UP(rate, 2 * miim->bus_freq) - 1; in mscc_miim_clk_set()
262 dev_err(&bus->dev, "Incorrect MDIO clock frequency\n"); in mscc_miim_clk_set()
263 return -EINVAL; in mscc_miim_clk_set()
266 return regmap_update_bits(miim->regs, MSCC_MIIM_REG_CFG, in mscc_miim_clk_set()
272 struct device_node *np = pdev->dev.of_node; in mscc_miim_probe()
274 struct device *dev = &pdev->dev; in mscc_miim_probe()
305 miim = bus->priv; in mscc_miim_probe()
306 miim->phy_regs = phy_regmap; in mscc_miim_probe()
308 miim->info = device_get_match_data(dev); in mscc_miim_probe()
309 if (!miim->info) in mscc_miim_probe()
310 return -EINVAL; in mscc_miim_probe()
312 miim->clk = devm_clk_get_optional(dev, NULL); in mscc_miim_probe()
313 if (IS_ERR(miim->clk)) in mscc_miim_probe()
314 return PTR_ERR(miim->clk); in mscc_miim_probe()
316 of_property_read_u32(np, "clock-frequency", &miim->bus_freq); in mscc_miim_probe()
318 if (miim->bus_freq && !miim->clk) { in mscc_miim_probe()
319 dev_err(dev, "cannot use clock-frequency without a clock\n"); in mscc_miim_probe()
320 return -EINVAL; in mscc_miim_probe()
323 ret = clk_prepare_enable(miim->clk); in mscc_miim_probe()
342 clk_disable_unprepare(miim->clk); in mscc_miim_probe()
349 struct mscc_miim_dev *miim = bus->priv; in mscc_miim_remove()
351 clk_disable_unprepare(miim->clk); in mscc_miim_remove()
368 .compatible = "mscc,ocelot-miim",
371 .compatible = "microchip,lan966x-miim",
382 .name = "mscc-miim",