| /linux-6.12.1/drivers/clk/hisilicon/ |
| D | clk-hi3620.c | 283 struct clk_mmc *mclk = to_mmc(hw); in mmc_clk_determine_rate() local
285 if ((req->rate <= 13000000) && (mclk->id == HI3620_MMC_CIUCLK1)) { in mmc_clk_determine_rate()
322 struct clk_mmc *mclk = to_mmc(hw); in mmc_clk_set_timing() local
359 val = readl_relaxed(mclk->clken_reg); in mmc_clk_set_timing()
360 val &= ~(1 << mclk->clken_bit); in mmc_clk_set_timing()
361 writel_relaxed(val, mclk->clken_reg); in mmc_clk_set_timing()
363 val = readl_relaxed(mclk->sam_reg); in mmc_clk_set_timing()
364 val = mmc_clk_delay(val, sam, mclk->sam_off, mclk->sam_bits); in mmc_clk_set_timing()
365 writel_relaxed(val, mclk->sam_reg); in mmc_clk_set_timing()
367 val = readl_relaxed(mclk->drv_reg); in mmc_clk_set_timing()
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| /linux-6.12.1/sound/soc/ti/ |
| D | davinci-evm.c | 25 struct clk *mclk; member
36 if (drvdata->mclk) in evm_startup()
37 return clk_prepare_enable(drvdata->mclk); in evm_startup()
49 clk_disable_unprepare(drvdata->mclk); in evm_shutdown()
180 struct clk *mclk; in davinci_evm_probe() local
206 mclk = devm_clk_get(&pdev->dev, "mclk"); in davinci_evm_probe()
207 if (PTR_ERR(mclk) == -EPROBE_DEFER) { in davinci_evm_probe()
209 } else if (IS_ERR(mclk)) { in davinci_evm_probe()
210 dev_dbg(&pdev->dev, "mclk not found.\n"); in davinci_evm_probe()
211 mclk = NULL; in davinci_evm_probe()
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| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | rv730_dpm.c | 118 LPRV7XX_SMC_MCLK_VALUE mclk) in rv730_populate_mclk_value() argument
183 mclk->mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv730_populate_mclk_value()
184 mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv730_populate_mclk_value()
185 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); in rv730_populate_mclk_value()
186 mclk->mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in rv730_populate_mclk_value()
187 mclk->mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2); in rv730_populate_mclk_value()
188 mclk->mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3); in rv730_populate_mclk_value()
189 mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss); in rv730_populate_mclk_value()
190 mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2); in rv730_populate_mclk_value()
294 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in rv730_populate_smc_acpi_state()
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| D | rv740_dpm.c | 114 DRM_DEBUG_KMS("Target MCLK greater than largest MCLK in DLL speed table\n"); in rv740_get_dll_speed()
187 RV7XX_SMC_MCLK_VALUE *mclk) in rv740_populate_mclk_value() argument
274 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv740_populate_mclk_value()
275 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv740_populate_mclk_value()
276 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv740_populate_mclk_value()
277 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv740_populate_mclk_value()
278 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv740_populate_mclk_value()
279 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv740_populate_mclk_value()
280 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv740_populate_mclk_value()
281 mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1); in rv740_populate_mclk_value()
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| D | rv770_dpm.c | 389 RV7XX_SMC_MCLK_VALUE *mclk) in rv770_populate_mclk_value() argument
474 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv770_populate_mclk_value()
475 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv770_populate_mclk_value()
476 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv770_populate_mclk_value()
477 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv770_populate_mclk_value()
478 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv770_populate_mclk_value()
479 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv770_populate_mclk_value()
480 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv770_populate_mclk_value()
593 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, in rv770_populate_mvdd_value() argument
604 if (mclk <= pi->mvdd_split_frequency) { in rv770_populate_mvdd_value()
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| D | cypress_dpm.c | 422 u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) in cypress_get_strobe_mode_settings() argument
429 if (mclk <= pi->mclk_strobe_mode_threshold) in cypress_get_strobe_mode_settings()
431 result = cypress_get_mclk_frequency_ratio(rdev, mclk, strobe_mode); in cypress_get_strobe_mode_settings()
474 RV7XX_SMC_MCLK_VALUE *mclk, in cypress_populate_mclk_value() argument
600 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in cypress_populate_mclk_value()
601 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in cypress_populate_mclk_value()
602 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in cypress_populate_mclk_value()
603 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in cypress_populate_mclk_value()
604 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in cypress_populate_mclk_value()
605 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in cypress_populate_mclk_value()
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| D | btc_dpm.c | 1214 u32 *sclk, u32 *mclk) in btc_skip_blacklist_clocks() argument
1218 if ((sclk == NULL) || (mclk == NULL)) in btc_skip_blacklist_clocks()
1225 (btc_blacklist_clocks[i].mclk == *mclk)) in btc_skip_blacklist_clocks()
1234 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk); in btc_skip_blacklist_clocks()
1244 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
1247 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
1250 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
1251 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
1254 (pl->mclk + in btc_adjust_clock_combinations()
1258 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
[all …]
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| /linux-6.12.1/sound/soc/mxs/ |
| D | mxs-sgtl5000.c | 25 u32 mclk; in mxs_sgtl5000_hw_params() local
31 mclk = 256 * rate; in mxs_sgtl5000_hw_params()
34 mclk = 512 * rate; in mxs_sgtl5000_hw_params()
38 /* Set SGTL5000's SYSCLK (provided by SAIF MCLK) */ in mxs_sgtl5000_hw_params()
39 ret = snd_soc_dai_set_sysclk(codec_dai, SGTL5000_SYSCLK, mclk, 0); in mxs_sgtl5000_hw_params()
42 mclk / 1000000, mclk / 1000 % 1000); in mxs_sgtl5000_hw_params()
46 /* The SAIF MCLK should be the same as SGTL5000_SYSCLK */ in mxs_sgtl5000_hw_params()
47 ret = snd_soc_dai_set_sysclk(cpu_dai, MXS_SAIF_MCLK, mclk, 0); in mxs_sgtl5000_hw_params()
50 mclk / 1000000, mclk / 1000 % 1000); in mxs_sgtl5000_hw_params()
141 * The Sgtl5000 sysclk is derived from saif0 mclk and it's range in mxs_sgtl5000_probe()
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| D | mxs-saif.c | 54 saif->mclk = freq; in mxs_saif_set_dai_sysclk()
74 * Set SAIF clock and MCLK
77 unsigned int mclk, in mxs_saif_set_clk() argument
84 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); in mxs_saif_set_clk()
109 * If MCLK is used, the SAIF clk ratio needs to match mclk ratio. in mxs_saif_set_clk()
113 * If MCLK is not used, we just set saif clk to 512*fs. in mxs_saif_set_clk()
120 switch (mclk / rate) { in mxs_saif_set_clk()
137 /* SAIF MCLK should be a sub-rate of 512x or 384x */ in mxs_saif_set_clk()
159 * Program the over-sample rate for MCLK output in mxs_saif_set_clk()
161 * The available MCLK range is 32x, 48x... 512x. The rate in mxs_saif_set_clk()
[all …]
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| /linux-6.12.1/sound/soc/qcom/qdsp6/ |
| D | q6prm.h | 67 /* Clock ID for MCLK for WSA2 core */
69 /* Clock ID for NPL MCLK for WSA2 core */
71 /* Clock ID for RX Core TX MCLK */
73 /* Clock ID for RX CORE TX 2X MCLK */
75 /* Clock ID for WSA core TX MCLK */
77 /* Clock ID for WSA core TX 2X MCLK */
79 /* Clock ID for WSA2 core TX MCLK */
81 /* Clock ID for WSA2 core TX 2X MCLK */
83 /* Clock ID for RX CORE MCLK2 2X MCLK */
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| /linux-6.12.1/sound/soc/rockchip/ |
| D | rk3399_gru_sound.c | 70 unsigned int mclk; in rockchip_sound_max98357a_hw_params() local
73 mclk = params_rate(params) * SOUND_FS; in rockchip_sound_max98357a_hw_params()
75 ret = snd_soc_dai_set_sysclk(snd_soc_rtd_to_cpu(rtd, 0), 0, mclk, 0); in rockchip_sound_max98357a_hw_params()
78 __func__, mclk, ret); in rockchip_sound_max98357a_hw_params()
91 unsigned int mclk; in rockchip_sound_rt5514_hw_params() local
94 mclk = params_rate(params) * SOUND_FS; in rockchip_sound_rt5514_hw_params()
96 ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk, in rockchip_sound_rt5514_hw_params()
104 mclk, SND_SOC_CLOCK_IN); in rockchip_sound_rt5514_hw_params()
123 int mclk, ret; in rockchip_sound_da7219_hw_params() local
125 /* in bypass mode, the mclk has to be one of the frequencies below */ in rockchip_sound_da7219_hw_params()
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| D | rockchip_spdif.c | 35 struct clk *mclk; member
71 clk_disable_unprepare(spdif->mclk); in rk_spdif_runtime_suspend()
82 ret = clk_prepare_enable(spdif->mclk); in rk_spdif_runtime_resume()
84 dev_err(spdif->dev, "mclk clock enable failed %d\n", ret); in rk_spdif_runtime_resume()
90 clk_disable_unprepare(spdif->mclk); in rk_spdif_runtime_resume()
100 clk_disable_unprepare(spdif->mclk); in rk_spdif_runtime_resume()
113 int srate, mclk; in rk_spdif_hw_params() local
117 mclk = srate * 128; in rk_spdif_hw_params()
134 ret = clk_set_rate(spdif->mclk, mclk); in rk_spdif_hw_params()
317 spdif->mclk = devm_clk_get(&pdev->dev, "mclk"); in rk_spdif_probe()
[all …]
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| /linux-6.12.1/sound/soc/meson/ |
| D | axg-tdm-interface.c | 107 if (!iface->mclk) { in axg_tdm_iface_set_sysclk()
110 ret = clk_set_rate(iface->mclk, freq); in axg_tdm_iface_set_sysclk()
125 if (!iface->mclk) { in axg_tdm_iface_set_fmt()
126 dev_err(dai->dev, "cpu clock master: mclk missing\n"); in axg_tdm_iface_set_fmt()
278 /* If no specific mclk is requested, default to bit clock * 2 */ in axg_tdm_iface_set_sclk()
279 clk_set_rate(iface->mclk, 2 * srate); in axg_tdm_iface_set_sclk()
281 /* Check if we can actually get the bit clock from mclk */ in axg_tdm_iface_set_sclk()
284 "can't derive sclk %lu from mclk %lu\n", in axg_tdm_iface_set_sclk()
483 ret = clk_prepare_enable(iface->mclk); in axg_tdm_iface_set_bias_level()
488 clk_disable_unprepare(iface->mclk); in axg_tdm_iface_set_bias_level()
[all …]
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| /linux-6.12.1/include/dt-bindings/sound/ |
| D | qcom,q6dsp-lpass-ports.h | 204 /* Clock ID for MCLK for WSA2 core */
206 /* Clock ID for NPL MCLK for WSA2 core */
208 /* Clock ID for RX Core TX MCLK */
210 /* Clock ID for RX CORE TX 2X MCLK */
212 /* Clock ID for WSA core TX MCLK */
214 /* Clock ID for WSA core TX 2X MCLK */
216 /* Clock ID for WSA2 core TX MCLK */
218 /* Clock ID for WSA2 core TX 2X MCLK */
220 /* Clock ID for RX CORE MCLK2 2X MCLK */
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| /linux-6.12.1/sound/soc/intel/boards/ |
| D | cht_bsw_rt5672.c | 27 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */
34 struct clk *mclk; member
66 if (ctx->mclk) { in platform_clock_control()
67 ret = clk_prepare_enable(ctx->mclk); in platform_clock_control()
70 "could not configure MCLK state"); in platform_clock_control()
75 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ in platform_clock_control()
92 * PLL will be off when idle and MCLK will also be off by ACPI in platform_clock_control()
103 if (ctx->mclk) in platform_clock_control()
104 clk_disable_unprepare(ctx->mclk); in platform_clock_control()
166 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ in cht_aif1_hw_params()
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| D | sof_rt5682.c | 34 /* Default: MCLK on, MCLK 19.2M, SSP0 */
152 dev_err(rtd->dev, "invalid mclk freq %d\n", mclk_freq); in sof_rt5682_codec_init()
156 /* need to enable ASRC function for 24MHz mclk rate */ in sof_rt5682_codec_init()
201 ret = clk_prepare_enable(ctx->rt5682.mclk); in sof_rt5682_codec_init()
203 clk_disable_unprepare(ctx->rt5682.mclk); in sof_rt5682_codec_init()
205 ret = clk_set_rate(ctx->rt5682.mclk, 19200000); in sof_rt5682_codec_init()
208 dev_err(rtd->dev, "unable to set MCLK rate\n"); in sof_rt5682_codec_init()
264 ret = clk_prepare_enable(ctx->rt5682.mclk); in sof_rt5682_hw_params()
267 "could not configure MCLK state"); in sof_rt5682_hw_params()
288 /* get the tplg configured mclk. */ in sof_rt5682_hw_params()
[all …]
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| /linux-6.12.1/sound/soc/codecs/ |
| D | es8311.c | 31 struct clk *mclk; member
326 unsigned int mclk; member
337 * settings. Internal mclk dividers and multipliers are dynamically adjusted to
340 * All rates are supported when mclk/rate ratio is 32, 64, 128, 256, 384 or 512
341 * (upper limit due to max mclk freq of 49.2MHz).
371 * If mclk_freq is a valid multiple or factor of coeff mclk freq, return 0 and
386 if (coeff->mclk == mclk_freq) { in es8311_cmp_adj_mclk_coeff()
388 } else if (mclk_freq % coeff->mclk == 0) { in es8311_cmp_adj_mclk_coeff()
389 div = mclk_freq / coeff->mclk; in es8311_cmp_adj_mclk_coeff()
393 } else if (coeff->mclk % mclk_freq == 0) { in es8311_cmp_adj_mclk_coeff()
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| D | nau8325.c | 25 /* Range of Master Clock MCLK (Hz) */
29 /* scaling for MCLK source */
35 /* from MCLK input */
70 /* { FS, range, max, { MCLK source }} */
344 int mclk, int *n2_sel) in nau8325_clksrc_n2() argument
350 mclk_src = mclk >> mclk_n2_div[i].param; in nau8325_clksrc_n2()
389 int i, j, mclk, mclk_max, ratio, ratio_sel, n2_max; in nau8325_clksrc_choose() local
391 if (!nau8325->mclk || !nau8325->fs) in nau8325_clksrc_choose()
399 /* First check clock from MCLK directly, decide N2 for MCLK_SRC. in nau8325_clksrc_choose()
402 ratio = nau8325_clksrc_n2(nau8325, *srate_table, nau8325->mclk, n2_sel); in nau8325_clksrc_choose()
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| D | cs4234.c | 36 struct clk *mclk; member
371 dev_err(component->dev, "Unsupported mclk/lrclk rate\n"); in cs4234_dai_hw_params()
427 /* Scale MCLK rate by 64 to avoid overflow in the ratnum calculation */
448 int mclk = cs4234->mclk_rate; in cs4234_dai_rule_rate() local
451 .min = mclk / clamp(mclk / 30000, 256, 512), in cs4234_dai_rule_rate()
452 .max = mclk / clamp(mclk / 50000, 256, 512), in cs4234_dai_rule_rate()
455 .min = mclk / clamp(mclk / 60000, 128, 256), in cs4234_dai_rule_rate()
456 .max = mclk / clamp(mclk / 100000, 128, 256), in cs4234_dai_rule_rate()
515 * MCLK/rate may be a valid ratio but out-of-spec (e.g. 24576000/64000) in cs4234_dai_startup()
516 * so this rule limits the range of sample rate for given MCLK. in cs4234_dai_startup()
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| D | lochnagar-sc.c | 20 struct clk *mclk; member
95 ret = clk_prepare_enable(priv->mclk); in lochnagar_sc_line_startup()
97 dev_err(dai->dev, "Failed to enable MCLK: %d\n", ret); in lochnagar_sc_line_startup()
116 clk_disable_unprepare(priv->mclk); in lochnagar_sc_line_shutdown()
232 priv->mclk = devm_clk_get(&pdev->dev, "mclk"); in lochnagar_sc_probe()
233 if (IS_ERR(priv->mclk)) { in lochnagar_sc_probe()
234 ret = PTR_ERR(priv->mclk); in lochnagar_sc_probe()
235 dev_err(&pdev->dev, "Failed to get MCLK: %d\n", ret); in lochnagar_sc_probe()
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| D | wm8731.c | 229 u32 mclk; member
237 /* codec mclk clock divider coefficients */
302 static inline int get_coeff(int mclk, int rate) in get_coeff() argument
307 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk) in get_coeff()
371 if (wm8731->mclk && clk_set_rate(wm8731->mclk, freq)) in wm8731_set_dai_sysclk()
473 if (wm8731->mclk) { in wm8731_set_bias_level()
474 ret = clk_prepare_enable(wm8731->mclk); in wm8731_set_bias_level()
496 if (wm8731->mclk) in wm8731_set_bias_level()
497 clk_disable_unprepare(wm8731->mclk); in wm8731_set_bias_level()
570 wm8731->mclk = devm_clk_get(dev, "mclk"); in wm8731_init()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/sound/ |
| D | mt8173-rt5650.txt | 16 - mediatek,mclk: the MCLK source
17 0 : external oscillator, MCLK = 12.288M
18 1 : internal source from mt8173, MCLK = sampling rate*256
26 mediatek,mclk = <0>;
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| D | qcom,lpass-tx-macro.yaml | 77 - const: mclk
83 - const: mclk
101 - const: mclk
119 - const: mclk
137 - const: mclk
157 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
158 clock-output-names = "mclk";
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| /linux-6.12.1/drivers/clk/ |
| D | clk-lochnagar.c | 50 LN_PARENT("ln-spdif-mclk"),
51 LN_PARENT("ln-psia1-mclk"),
52 LN_PARENT("ln-psia2-mclk"),
67 LN_PARENT("ln-spdif-mclk"),
77 LN_PARENT("ln-psia1-mclk"),
78 LN_PARENT("ln-psia2-mclk"),
80 LN_PARENT("ln-adat-mclk"),
115 LN2_CLK(PSIA1_MCLK, "ln-psia1-mclk"),
116 LN2_CLK(PSIA2_MCLK, "ln-psia2-mclk"),
117 LN2_CLK(SPDIF_MCLK, "ln-spdif-mclk"),
[all …]
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| /linux-6.12.1/sound/soc/stm/ |
| D | stm32_i2s.c | 214 * @i2smclk: master clock from I2S mclk provider
338 struct stm32_i2smclk_data *mclk = to_mclk_data(hw); in stm32_i2smclk_round_rate() local
339 struct stm32_i2s_data *i2s = mclk->i2s_data; in stm32_i2smclk_round_rate()
346 mclk->freq = *prate / i2s->divider; in stm32_i2smclk_round_rate()
348 return mclk->freq; in stm32_i2smclk_round_rate()
354 struct stm32_i2smclk_data *mclk = to_mclk_data(hw); in stm32_i2smclk_recalc_rate() local
356 return mclk->freq; in stm32_i2smclk_recalc_rate()
362 struct stm32_i2smclk_data *mclk = to_mclk_data(hw); in stm32_i2smclk_set_rate() local
363 struct stm32_i2s_data *i2s = mclk->i2s_data; in stm32_i2smclk_set_rate()
374 mclk->freq = rate; in stm32_i2smclk_set_rate()
[all …]
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