25 /* Range of Master Clock MCLK (Hz) */
29 /* scaling for MCLK source */
35 /* from MCLK input */
70 	/* { FS, range, max, { MCLK source }} */
344 			     int mclk, int *n2_sel)  in nau8325_clksrc_n2()  argument
350 		mclk_src = mclk >> mclk_n2_div[i].param;  in nau8325_clksrc_n2()
389 	int i, j, mclk, mclk_max, ratio, ratio_sel, n2_max;  in nau8325_clksrc_choose()  local
391 	if (!nau8325->mclk || !nau8325->fs)  in nau8325_clksrc_choose()
399 	/* First check clock from MCLK directly, decide N2 for MCLK_SRC.  in nau8325_clksrc_choose()
402 	ratio = nau8325_clksrc_n2(nau8325, *srate_table, nau8325->mclk, n2_sel);  in nau8325_clksrc_choose()
414 			mclk = nau8325->mclk << mclk_n3_mult[j].param;  in nau8325_clksrc_choose()
415 			mclk = mclk / mclk_n1_div[i].param;  in nau8325_clksrc_choose()
417 						  *srate_table, mclk, n2_sel);  in nau8325_clksrc_choose()
419 			    (mclk_max < mclk || i > *n1_sel)) {  in nau8325_clksrc_choose()
420 				mclk_max = mclk;  in nau8325_clksrc_choose()
436 	dev_dbg(nau8325->dev, "The MCLK %d is invalid. It can't get MCLK_SRC of 256/400/500 FS (%d)",  in nau8325_clksrc_choose()
437 		nau8325->mclk, nau8325->fs);  in nau8325_clksrc_choose()
610 		dev_dbg(nau8325->dev, "MCLK exceeds the range, MCLK:%d", freq);  in nau8325_set_sysclk()
614 	nau8325->mclk = freq;  in nau8325_set_sysclk()
615 	dev_dbg(nau8325->dev, "MCLK %dHz", nau8325->mclk);  in nau8325_set_sysclk()