31 	struct clk *mclk;  member
326 	unsigned int mclk;  member
337  * settings. Internal mclk dividers and multipliers are dynamically adjusted to
340  * All rates are supported when mclk/rate ratio is 32, 64, 128, 256, 384 or 512
341  * (upper limit due to max mclk freq of 49.2MHz).
371  * If mclk_freq is a valid multiple or factor of coeff mclk freq, return 0 and
386 	if (coeff->mclk == mclk_freq) {  in es8311_cmp_adj_mclk_coeff()
388 	} else if (mclk_freq % coeff->mclk == 0) {  in es8311_cmp_adj_mclk_coeff()
389 		div = mclk_freq / coeff->mclk;  in es8311_cmp_adj_mclk_coeff()
393 	} else if (coeff->mclk % mclk_freq == 0) {  in es8311_cmp_adj_mclk_coeff()
394 		mult = coeff->mclk / mclk_freq;  in es8311_cmp_adj_mclk_coeff()
522 		dev_err(component->dev, "mclk frequency %lu too high\n",  in es8311_hw_params()
534 				"mclk not configured, cannot run as master\n");  in es8311_hw_params()
538 			"mclk not configured, use bclk as internal mclk\n");  in es8311_hw_params()
548 		dev_err(component->dev, "unable to find mclk coefficient\n");  in es8311_hw_params()
608 				"unable to divide mclk %u to generate bclk\n",  in es8311_hw_params()
663 	int ret = clk_set_rate(es8311->mclk, freq);  in es8311_set_sysclk()
665 		dev_err(component->dev, "unable to set mclk rate\n");  in es8311_set_sysclk()
771 			int ret = clk_prepare_enable(es8311->mclk);  in es8311_set_bias_level()
774 					"unable to prepare mclk\n");  in es8311_set_bias_level()
786 		clk_disable_unprepare(es8311->mclk);  in es8311_set_bias_level()
881 	es8311->mclk = devm_clk_get_optional(component->dev, "mclk");  in es8311_component_probe()
882 	if (IS_ERR(es8311->mclk)) {  in es8311_component_probe()
883 		dev_err(component->dev, "invalid mclk\n");  in es8311_component_probe()
884 		return PTR_ERR(es8311->mclk);  in es8311_component_probe()
887 	es8311->mclk_freq = clk_get_rate(es8311->mclk);  in es8311_component_probe()