27 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */
34 	struct clk *mclk;  member
66 		if (ctx->mclk) {  in platform_clock_control()
67 			ret = clk_prepare_enable(ctx->mclk);  in platform_clock_control()
70 					"could not configure MCLK state");  in platform_clock_control()
75 		/* set codec PLL source to the 19.2MHz platform clock (MCLK) */  in platform_clock_control()
92 		 * PLL will be off when idle and MCLK will also be off by ACPI  in platform_clock_control()
103 		if (ctx->mclk)  in platform_clock_control()
104 			clk_disable_unprepare(ctx->mclk);  in platform_clock_control()
166 	/* set codec PLL source to the 19.2MHz platform clock (MCLK) */  in cht_aif1_hw_params()
242 	if (ctx->mclk) {  in cht_codec_init()
253 		ret = clk_prepare_enable(ctx->mclk);  in cht_codec_init()
255 			clk_disable_unprepare(ctx->mclk);  in cht_codec_init()
257 		ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ);  in cht_codec_init()
260 			dev_err(runtime->dev, "unable to set MCLK rate\n");  in cht_codec_init()
506 	drv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3");  in snd_cht_mc_probe()
507 	if (IS_ERR(drv->mclk)) {  in snd_cht_mc_probe()
509 			"Failed to get MCLK from pmc_plt_clk_3: %ld\n",  in snd_cht_mc_probe()
510 			PTR_ERR(drv->mclk));  in snd_cht_mc_probe()
511 		return PTR_ERR(drv->mclk);  in snd_cht_mc_probe()