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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dapple,aic2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
21 - Software triggering (ORed with hw line)
22 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
[all …]
Dst,stih407-irq-syscfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 On STi based systems; External, CTI (Core Sight), PMU (Performance
19 const: st,stih407-irq-syscfg
22 description: Phandle to Cortex-A9 IRQ system config registers
25 st,irq-device:
27 $ref: /schemas/types.yaml#/definitions/uint32-array
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/linux-6.12.1/arch/arm/mach-omap1/
Dams-delta-fiq-handler.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S
5 * Based on linux/arch/arm/lib/floppydma.S
14 #include <linux/platform_data/ams-delta-fiq.h>
15 #include <linux/platform_data/gpio-omap.h>
16 #include <linux/soc/ti/omap1-io.h>
22 #include "ams-delta-fiq.h"
23 #include "board-ams-delta.h"
27 * OMAP1510 GPIO related symbol copied from arch/arm/mach-omap1/gpio15xx.c.
79 * r8 - temporary
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
24 bool "OMAP15xx Based System"
30 bool "OMAP16xx Based System"
73 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
86 timer provides more intra-tick resolution than the 32KHz timer,
90 bool "Enable wake-up events for serial ports"
153 select FIQ
Dboard-ams-delta.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/board-ams-delta.c
5 * Modified from board-generic.c
19 #include <linux/mtd/nand-gpio.h>
29 #include <linux/platform_data/gpio-omap.h>
30 #include <linux/soc/ti/omap1-mux.h>
33 #include <asm/mach-types.h>
37 #include <linux/platform_data/keypad-omap.h>
41 #include "ams-delta-fiq.h"
42 #include "board-ams-delta.h"
[all …]
/linux-6.12.1/drivers/irqchip/
Dirq-apple-aic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on irq-lpc32xx:
6 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
7 * Based on irq-bcm2836:
14 * - 896 level-triggered hardware IRQs
15 * - Single mask bit per IRQ
16 * - Per-IRQ affinity setting
17 * - Automatic masking on event delivery (auto-ack)
18 * - Software triggering (ORed with hw line)
19 * - 2 per-CPU IPIs (meant as "self" and "other", but they are
[all …]
Dirq-ixp4xx.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on arch/arm/mach-ixp4xx/common.c
8 * Copyright 2003-2004 (C) MontaVista, Software, Inc.
28 #define IXP4XX_ICLR 0x08 /* Interrupt IRQ/FIQ Select */
30 #define IXP4XX_ICFP 0x10 /* FIQ Status */
33 #define IXP4XX_ICFH 0x1C /* FIQ Highest Pri Int */
35 /* IXP43x and IXP46x-only */
38 #define IXP4XX_ICLR2 0x28 /* Interrupt IRQ/FIQ Select 2 */
40 #define IXP4XX_ICFP2 0x30 /* FIQ Status */
44 * struct ixp4xx_irq - state container for the Faraday IRQ controller
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Dirq-sa11x0.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Dmitry Eremin-Solenikov
4 * Copyright (C) 1999-2001 Nicolas Pitre
15 #include <linux/irqchip/irq-sa11x0.h>
25 #define ICFP 0x10 /* IC FIQ Pending reg. */
39 reg &= ~BIT(d->hwirq); in sa1100_mask_irq()
48 reg |= BIT(d->hwirq); in sa1100_unmask_irq()
54 return sa11x0_sc_set_wake(d->hwirq, on); in sa1100_set_wake()
92 st->saved = 1; in sa1100irq_suspend()
93 st->icmr = readl_relaxed(iobase + ICMR); in sa1100irq_suspend()
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Dirq-gic-v3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
26 #include <linux/irqchip/arm-gic-common.h>
27 #include <linux/irqchip/arm-gic-v3.h>
28 #include <linux/irqchip/arm-gic-v3-prio.h>
29 #include <linux/irqchip/irq-partition-percpu.h>
32 #include <linux/arm-smccc.h>
39 #include "irq-gic-common.h"
95 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
99 * When security is enabled, non-secure priority values from the (re)distributor
[all …]
/linux-6.12.1/arch/arm64/kernel/
Dirq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/kernel/irq.c
6 * Modifications for ARM processor Copyright (C) 1995-2000 Russell King.
7 * Support for Dynamic Tick Timer Copyright (C) 2004-2005 Nokia Corporation.
66 /* irq stack only needs to be 16 byte aligned - not IRQ_STACK_SIZE aligned. */
97 panic("FIQ taken without a root FIQ handler\n"); in default_handle_fiq()
106 return -EBUSY; in set_handle_irq()
116 return -EBUSY; in set_handle_fiq()
119 pr_info("Root FIQ handler: %ps\n", handle_fiq); in set_handle_fiq()
Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/kernel/setup.c
5 * Copyright (C) 1995-2001 Russell King
105 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
115 * Pre-scan the list of MPIDRS and filter out bits that do in smp_build_mpidr_hash()
133 fs[i] = affinity ? ffs(affinity) - 1 : 0; in smp_build_mpidr_hash()
134 bits[i] = ls - fs[i]; in smp_build_mpidr_hash()
147 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; in smp_build_mpidr_hash()
148 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - in smp_build_mpidr_hash()
151 fs[3] - (bits[2] + bits[1] + bits[0]); in smp_build_mpidr_hash()
[all …]
/linux-6.12.1/sound/soc/fsl/
Dimx-pcm-fiq.c1 // SPDX-License-Identifier: GPL-2.0+
2 // imx-pcm-fiq.c -- ALSA Soc Audio Layer
6 // This code is based on code copyrighted by Freescale,
12 #include <linux/dma-mapping.h>
26 #include <asm/fiq.h>
28 #include <linux/platform_data/asoc-imx-ssi.h>
30 #include "imx-ssi.h"
31 #include "imx-pcm.h"
48 struct snd_pcm_substream *substream = iprtd->substream; in snd_hrtimer_callback()
51 if (!atomic_read(&iprtd->playing) && !atomic_read(&iprtd->capturing)) in snd_hrtimer_callback()
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Dimx-pcm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * This code is based on code copyrighted by Freescale,
12 #include <linux/dma/imx-dma.h>
15 * Do not change this as the FIQ handler depends on this size
35 return -ENODEV; in imx_pcm_dma_init()
47 return -ENODEV; in imx_pcm_fiq_init()
Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
17 // manually skip this data in the FIQ handler. With sampling rates different
19 // between pcm data and GPIO status data changes. Our FIQ handler is not
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
66 * (bit-endianness must match byte-endianness). Processors typically write
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 This option is only useful for out-of-tree drivers since
15 in-tree drivers select it automatically.
26 This option is only useful for out-of-tree drivers since
27 in-tree drivers select it automatically.
36 This option is only useful for out-of-tree drivers since
37 in-tree drivers select it automatically.
54 This option is only useful for out-of-tree drivers since
55 in-tree drivers select it automatically.
67 This option is only useful for out-of-tree drivers since
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/linux-6.12.1/fs/fuse/
Dinode.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
78 sl->forget = fuse_alloc_forget(); in fuse_alloc_submount_lookup()
79 if (!sl->forget) in fuse_alloc_submount_lookup()
97 fi->i_time = 0; in fuse_alloc_inode()
98 fi->inval_mask = ~0; in fuse_alloc_inode()
99 fi->nodeid = 0; in fuse_alloc_inode()
100 fi->nlookup = 0; in fuse_alloc_inode()
101 fi->attr_version = 0; in fuse_alloc_inode()
102 fi->orig_ino = 0; in fuse_alloc_inode()
103 fi->state = 0; in fuse_alloc_inode()
[all …]
Dfuse_i.h3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
23 #include <linux/backing-dev.h>
41 /** Bias for fi->writectr, meaning new writepages must not be sent */
110 /** The sticky bit in inode->i_mode may have been removed, so
126 /* Files usable in writepage. Protected by fi->lock */
142 /* waitq for direct-io completion */
257 /** RB node to be linked on fuse_conn->polled_files */
263 /** Does file hold a fi->iocachectr refcount? */
398 * - FR_ABORTED
399 * - FR_LOCKED (may also be modified under fc->lock, tested under both)
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/linux-6.12.1/Documentation/arch/arm64/
Dbooting.rst9 This document is based on the ARM booting document by Russell King and
13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
33 ---------------------------
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
91 - As of v3.17, all fields are little endian unless stated otherwise.
93 - code0/code1 are responsible for branching to stext.
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/linux-6.12.1/arch/arm64/kvm/hyp/
Dexception.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012,2013 - ARM Ltd
8 * Based on arch/arm/kvm/emulate.c
9 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
63 vcpu->arch.ctxt.spsr_abt = val; in __vcpu_write_spsr_abt()
71 vcpu->arch.ctxt.spsr_und = val; in __vcpu_write_spsr_und()
77 * The EL passed to this function *must* be a non-secure, privileged mode with
85 * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429.
86 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
134 if (kvm_has_mte(kern_hyp_va(vcpu->kvm))) in enter_exception64()
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/linux-6.12.1/arch/arm/include/asm/
Dptrace.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2003 Russell King
29 (((regs)->ARM_cpsr & 0xf) == 0)
33 (((regs)->ARM_cpsr & PSR_T_BIT))
40 (FIELD_GET(PSR_J_BIT, (regs)->ARM_cpsr) << 1 | \
41 FIELD_GET(PSR_T_BIT, (regs)->ARM_cpsr))
47 ((regs)->ARM_cpsr & MODE_MASK)
50 (!((regs)->ARM_cpsr & PSR_I_BIT))
53 (!((regs)->ARM_cpsr & PSR_F_BIT))
61 unsigned long mode = regs->ARM_cpsr & MODE_MASK; in valid_user_regs()
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/linux-6.12.1/arch/arm64/include/asm/
Dkvm_arm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
150 * We configure the Stage-2 page tables to always restrict the IPA space to be
169 * -----------------------------------------
171 * ------------------------------------------
172 * | Level: 0 | 2 | - |
173 * ------------------------------------------
175 * ------------------------------------------
177 * ------------------------------------------
178 * | Level: 3 | - | 0 |
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/linux-6.12.1/tools/perf/pmu-events/arch/x86/elkhartlake/
Dpipeline.json89 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address…
223 … to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.…
274 …ounts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stor…
355 … consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation …
474 …he number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops a…
495 …tion": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
/linux-6.12.1/tools/perf/pmu-events/arch/x86/snowridgex/
Dpipeline.json89 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address…
223 … to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.…
274 …ounts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stor…
355 … consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation …
474 …he number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops a…
495 …tion": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
/linux-6.12.1/tools/perf/pmu-events/arch/x86/sierraforest/
Dpipeline.json89 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address…
200 … to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.…
232 …ounts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stor…
342 …ere not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IE…
487 …he number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops a…
506 …ounts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This…
/linux-6.12.1/tools/perf/pmu-events/arch/x86/grandridge/
Dpipeline.json89 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address…
200 … to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.…
232 …ounts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stor…
342 …ere not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IE…
487 …he number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops a…
506 …ounts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This…

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