Lines Matching +full:fiq +full:- +full:based
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2003 Russell King
29 (((regs)->ARM_cpsr & 0xf) == 0)
33 (((regs)->ARM_cpsr & PSR_T_BIT))
40 (FIELD_GET(PSR_J_BIT, (regs)->ARM_cpsr) << 1 | \
41 FIELD_GET(PSR_T_BIT, (regs)->ARM_cpsr))
47 ((regs)->ARM_cpsr & MODE_MASK)
50 (!((regs)->ARM_cpsr & PSR_I_BIT))
53 (!((regs)->ARM_cpsr & PSR_F_BIT))
61 unsigned long mode = regs->ARM_cpsr & MODE_MASK; in valid_user_regs()
64 * Always clear the F (FIQ) and A (delayed abort) bits in valid_user_regs()
66 regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); in valid_user_regs()
68 if ((regs->ARM_cpsr & PSR_I_BIT) == 0) { in valid_user_regs()
78 regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT; in valid_user_regs()
80 regs->ARM_cpsr |= USR_MODE; in valid_user_regs()
90 return regs->ARM_r0; in regs_return_value()
93 #define instruction_pointer(regs) (regs)->ARM_pc
96 #define frame_pointer(regs) (regs)->ARM_r7
98 #define frame_pointer(regs) (regs)->ARM_fp
117 * True if instr is a 32-bit thumb instruction. This works if instr
118 * is the first or only half-word of a thumb instruction. It also works
119 * when instr holds all 32-bits of a wide thumb instruction if stored
125 * kprobe-based event tracer support
137 * regs_get_register() - get register value from its offset
156 return regs->ARM_sp; in kernel_stack_pointer()
161 return regs->ARM_sp; in user_stack_pointer()
165 ((current_stack_pointer | (THREAD_SIZE - 1)) - 7) - 1; \
170 regs->ARM_r0 = rc; in regs_set_return_value()
190 it |= it >> (27 - 10); /* Carry ITSTATE<2> to correct place */ in it_advance()