arch/arm64/booting.rst

9 This document is based on the ARM booting document by Russell King and
13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
33 ---------------------------
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
91 - As of v3.17, all fields are little endian unless stated otherwise.
93 - code0/code1 are responsible for branching to stext.
95 - when booting through EFI, code0/code1 are initially skipped.
100 - Prior to v3.17, the endianness of text_offset was not specified.  In
102   endianness of the kernel.  Where image_size is non-zero image_size is
103   little-endian and must be respected.  Where image_size is zero,
106 - The flags field (introduced in v3.17) is a little-endian 64-bit field
111   Bit 1-2	Kernel Page size.
113 			* 0 - Unspecified.
114 			* 1 - 4K
115 			* 2 - 16K
116 			* 3 - 64K
126 			  the 48-bit addressable range of physical memory
127   Bits 4-63	Reserved.
130 - When image_size is zero, a bootloader should attempt to keep as much
156 - Quiesce all DMA capable devices so that memory does not get
160 - Primary CPU general-purpose register settings:
162     - x0 = physical address of device tree blob (dtb) in system RAM.
163     - x1 = 0 (reserved for future use)
164     - x2 = 0 (reserved for future use)
165     - x3 = 0 (reserved for future use)
167 - CPU mode
170   IRQ and FIQ).
171   The CPU must be in non-secure state, either in EL2 (RECOMMENDED in order
174 - Caches, MMUs
190 - Architected timers
197 - Coherency
204 - System registers
212   - If EL3 is present:
214     - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
216     - The value of SCR_EL3.FIQ must be the same as the one present at boot
219   - If EL3 is present and the kernel is entered at EL2:
221     - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
224   - If EL3 is present:
226       - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
227       - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
228       - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
232   - If the kernel is entered at EL1:
234       - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
235       - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
237   - The DT or ACPI tables must describe a GICv3 interrupt controller.
242   - If EL3 is present:
246   - If the kernel is entered at EL1:
250   - The DT or ACPI tables must describe a GICv2 interrupt controller.
254   - If EL3 is present:
256     - SCR_EL3.APK (bit 16) must be initialised to 0b1
257     - SCR_EL3.API (bit 17) must be initialised to 0b1
259   - If the kernel is entered at EL1:
261     - HCR_EL2.APK (bit 40) must be initialised to 0b1
262     - HCR_EL2.API (bit 41) must be initialised to 0b1
266   - If EL3 is present:
268     - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
269     - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
270     - AMCNTENSET0_EL0 must be initialised to 0b1111
271     - AMCNTENSET1_EL0 must be initialised to a platform specific value
275   - If the kernel is entered at EL1:
277     - AMCNTENSET0_EL0 must be initialised to 0b1111
278     - AMCNTENSET1_EL0 must be initialised to a platform specific value
284   - If EL3 is present and the kernel is entered at EL2:
286     - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
290   - If EL3 is present and the kernel is entered at EL2:
292     - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
296   - If EL3 is present:
298     - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
300   - If EL2 is present and the kernel is entered at EL1:
302     - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
306   - if EL3 is present:
308     - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
310     - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
313   - If the kernel is entered at EL1 and EL2 is present:
315     - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
317     - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
319     - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
324   - If EL3 is present:
326     - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
328     - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
330     - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
333  - If the kernel is entered at EL1 and EL2 is present:
335     - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
337     - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
339     - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
341     - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
344     - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
346     - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
348     - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
350     - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
354   - If EL3 is present:
356     - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
358  - If the kernel is entered at EL1 and EL2 is present:
360     - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
364   - If EL3 is present:
366     - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
368   - If the kernel is entered at EL1 and EL2 is present:
370     - HCR_EL2.ATA (bit 56) must be initialised to 0b1.
374   - If EL3 is present:
376     - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.
378  - If the kernel is entered at EL1 and EL2 is present:
380     - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
384   - If the kernel is entered at EL1 and EL2 is present:
386     - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1.
390   - If EL3 is present:
392     - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1.
394  - If the kernel is entered at EL1 and EL2 is present:
396     - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1.
400   - If EL3 is present:
402     - SCR_EL3.PIEn (bit 45) must be initialised to 0b1.
404   - If the kernel is entered at EL1 and EL2 is present:
406     - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
408     - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
410     - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
412     - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
424 - The primary CPU must jump directly to the first instruction of the
426   an 'enable-method' property for each cpu node.  The supported
427   enable-methods are described below.
432 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
434   naturally-aligned 64-bit zero-initalised memory location.
438   device tree) polling their cpu-release-addr location, which must be
440   to reduce the overhead of the busy-loop and a sev will be issued by
442   cpu-release-addr returns a non-zero value, the CPU must jump to this
443   value.  The value will be written as a single 64-bit little-endian
447 - CPUs with a "psci" enable method should remain outside of
458 - Secondary CPU general-purpose register settings
460   - x0 = 0 (reserved for future use)
461   - x1 = 0 (reserved for future use)
462   - x2 = 0 (reserved for future use)
463   - x3 = 0 (reserved for future use)