include/asm/kvm_arm.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (C) 2012,2013 - ARM Ltd
150  * We configure the Stage-2 page tables to always restrict the IPA space to be
169  *	-----------------------------------------
171  *	------------------------------------------
172  *	| Level: 0		|  2   |   -     |
173  *	------------------------------------------
175  *	------------------------------------------
177  *	------------------------------------------
178  *	| Level: 3		|  -   |   0     |
179  *	------------------------------------------
183  *	SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level
190  * Entry_Level = 4 - Number_of_levels.
211 	((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
213 	((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
218 #define VTCR_EL2_IPA(vtcr)		(64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
221  * ARM VMSAv8-64 defines an algorithm for finding the translation table
225  * addresses for each level, based on PAGE_SIZE, entry level
231  * depending on the T0SZ, the value of "x" is defined based on a
237  *    x = Magic_N - T0SZ
242  *	--------------------------------------------
244  *	--------------------------------------------
245  *	| Level: 0 (4 levels)	| 28   |  -  |  -  |
246  *	--------------------------------------------
248  *	--------------------------------------------
250  *	--------------------------------------------
251  *	| Level: 3 (1 level)	| -    | 53  | 51  |
252  *	--------------------------------------------
256  *  Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels)
258  * where Number_of_levels = (4 - Level). We are only interested in the
261  * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows:
263  *	x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT)
264  *	  = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
270  * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
273  *  Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
274  *		     = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3
278  *    = IPA_SHIFT - (PAGE_SHIFT - 3) * n
283 #define ARM64_VTTBR_X(ipa, levels)	((ipa) - ((levels) * (PAGE_SHIFT - 3)))
287 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
399  *	PAR	[PA_Shift - 1	: 12] = PA	[PA_Shift - 1 : 12]
400  *	HPFAR	[PA_Shift - 9	: 4]  = FIPA	[PA_Shift - 1 : 12]
407 	(((par) & GENMASK_ULL(52 - 1, 12)) >> 8)
432 	{ PSR_AA32_MODE_USR,	"32-bit USR" },	\
433 	{ PSR_AA32_MODE_FIQ,	"32-bit FIQ" },	\
434 	{ PSR_AA32_MODE_IRQ,	"32-bit IRQ" },	\
435 	{ PSR_AA32_MODE_SVC,	"32-bit SVC" },	\
436 	{ PSR_AA32_MODE_ABT,	"32-bit ABT" },	\
437 	{ PSR_AA32_MODE_HYP,	"32-bit HYP" },	\
438 	{ PSR_AA32_MODE_UND,	"32-bit UND" },	\
439 	{ PSR_AA32_MODE_SYS,	"32-bit SYS" }