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/linux-6.12.1/include/linux/
Dmath64.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #if BITS_PER_LONG == 64
16 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
17 * @dividend: unsigned 64bit dividend
18 * @divisor: unsigned 32bit divisor
19 * @remainder: pointer to unsigned 32bit remainder
23 * This is commonly provided by 32bit archs to provide an optimized 64bit
33 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
34 * @dividend: signed 64bit dividend
35 * @divisor: signed 32bit divisor
[all …]
Dexportfs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 * 32bit inode number, 32 bit generation number.
38 * 32bit inode number, 32 bit generation number,
39 * 32 bit parent directory inode number.
44 * 64 bit object ID, 64 bit root object ID,
45 * 32 bit generation number.
50 * 64 bit object ID, 64 bit root object ID,
51 * 32 bit generation number,
52 * 64 bit parent object ID, 32 bit parent generation.
57 * 64 bit object ID, 64 bit root object ID,
[all …]
/linux-6.12.1/drivers/mtd/nand/raw/
Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
[all …]
/linux-6.12.1/arch/x86/crypto/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 depends on X86 && 64BIT
14 - ADX (large integer arithmetic)
17 tristate "Ciphers: AES, modes: ECB, CBC, CTS, CTR, XCTR, XTS, GCM (AES-NI/VAES)"
28 Length-preserving ciphers: AES with ECB, CBC, CTS, CTR, XCTR, XTS
30 Architecture: x86 (32-bit and 64-bit) using:
31 - AES-NI (AES new instructions)
32 - VAES (Vector AES)
34 Some algorithm implementations are supported only in 64-bit builds,
39 depends on X86 && 64BIT
[all …]
/linux-6.12.1/lib/
Datomic64_test.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #define TEST(bit, op, c_op, val) \ argument
22 atomic##bit##_set(&v, v0); \
24 atomic##bit##_##op(val, &v); \
26 WARN(atomic##bit##_read(&v) != r, "%Lx != %Lx\n", \
27 (unsigned long long)atomic##bit##_read(&v), \
33 * @test should be a macro accepting parameters (bit, op, ...)
36 #define FAMILY_TEST(test, bit, op, args...) \ argument
38 test(bit, op, ##args); \
39 test(bit, op##_acquire, ##args); \
[all …]
/linux-6.12.1/arch/parisc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T if !64BIT
20 select ARCH_SPLIT_ARG64 if !64BIT
40 select GENERIC_ATOMIC64 if !64BIT
83 select HAVE_DYNAMIC_FTRACE if $(cc-option,-fpatchable-function-entry=1,1)
90 select HAVE_FUNCTION_DESCRIPTORS if 64BIT
94 The PA-RISC microprocessor is designed by Hewlett-Packard and used
96 and later HP3000 series). The PA-RISC Linux project home page is
124 select GENERIC_BUG_RELATIVE_POINTERS if 64BIT
143 default 18 if 64BIT
[all …]
/linux-6.12.1/drivers/net/ethernet/cavium/liquidio/
Dcn23xx_pf_regs.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
74 /* 2 scatch registers (64-bit) */
80 /* 1 registers (64-bit) - SLI_CTL_STATUS */
83 /* SLI Packet Input Jabber Register (64 bit register)
117 /* 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
122 /*1 register (64-bit) to determine whether IOQs are in reset. */
125 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
141 /* Starting bit of the TRS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
143 /* Starting bit of SRN field in CN23XX_SLI_PKT_MAC_RINFO64 register */
[all …]
Dcn23xx_vf_regs.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
47 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
52 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
55 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
58 /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
61 /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
64 /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data &
69 /*------- Request Queue Macros ---------*/
85 /*------------------ Masks ----------------*/
[all …]
/linux-6.12.1/drivers/gpio/
Dgpio-xilinx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2008 - 2013 Xilinx, Inc.
31 #define XGPIO_GIER_IE BIT(31)
45 * struct xgpio_instance - Stores information about GPIO device
63 DECLARE_BITMAP(hw_map, 64);
64 DECLARE_BITMAP(sw_map, 64);
65 DECLARE_BITMAP(state, 64);
66 DECLARE_BITMAP(last_irq_read, 64);
67 DECLARE_BITMAP(dir, 64);
70 DECLARE_BITMAP(enable, 64);
[all …]
/linux-6.12.1/arch/x86/um/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
14 config 64BIT config
15 bool "64-bit kernel" if "$(SUBARCH)" = "x86"
19 def_bool !64BIT
28 def_bool 64BIT
32 bool "Three-level pagetables" if !64BIT
33 default 64BIT
35 Three-level pagetables will let UML have more than 4G of physical
39 However, this it experimental on 32-bit architectures, so if unsure say
40 N (on x86-64 it's automatically enabled, instead, as it's safe there).
[all …]
/linux-6.12.1/drivers/net/ethernet/broadcom/
Dtg3.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Copyright (C) 2007-2016 Broadcom Corporation.
9 * Copyright (C) 2016-2017 Broadcom Limited.
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
78 /* 0x04 --> 0x2c unused */
115 /* 0x30 --> 0x64 unused */
117 /* 0x66 --> 0x68 unused */
284 /* 0x94 --> 0x98 unused */
[all …]
/linux-6.12.1/arch/riscv/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
7 config 64BIT config
10 config 32BIT
36 select ARCH_HAS_KERNEL_FPU_SUPPORT if 64BIT && FPU
43 select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
55 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE if 64BIT && MMU
63 # LLD >= 14: https://github.com/llvm/llvm-project/issues/50505
70 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
79 select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
[all …]
/linux-6.12.1/drivers/acpi/acpica/
Dtbfadt.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: tbfadt - FADT table utilities
6 * Copyright (C) 2000 - 2023, Intel Corp.
143 * PARAMETERS: generic_address - GAS struct to be initialized
144 * space_id - ACPI Space ID for this register
145 * byte_width - Width of this register
146 * address - Address of the register
147 * register_name - ASCII name of the ACPI register
166 * Bit width field in the GAS is only one byte long, 255 max. in acpi_tb_init_generic_address()
178 "%s - 32-bit FADT register is too long (%u bytes, %u bits) " in acpi_tb_init_generic_address()
[all …]
/linux-6.12.1/lib/math/
Ddiv64.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on former do_div() implementation from asm-parisc/div64.h:
6 * Copyright (C) 1999 Hewlett-Packard Co
7 * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
10 * Generic C version of 64bit/32bit division and modulo, with
11 * 64bit result and 32bit remainder.
16 * for some CPUs. __div64_32() can be overridden by linking arch-specific
28 /* Not needed on 64bit architectures */
39 /* Reduce the thing a bit first */ in __div64_32()
44 rem -= (uint64_t) (high*base) << 32; in __div64_32()
[all …]
/linux-6.12.1/arch/s390/include/asm/
Delf.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Derived from "include/asm-i386/elf.h"
13 #define R_390_8 1 /* Direct 8 bit. */
14 #define R_390_12 2 /* Direct 12 bit. */
15 #define R_390_16 3 /* Direct 16 bit. */
16 #define R_390_32 4 /* Direct 32 bit. */
17 #define R_390_PC32 5 /* PC relative 32 bit. */
18 #define R_390_GOT12 6 /* 12 bit GOT offset. */
19 #define R_390_GOT32 7 /* 32 bit GOT offset. */
20 #define R_390_PLT32 8 /* 32 bit PC relative PLT address. */
[all …]
/linux-6.12.1/include/xen/interface/
Dcallback.h1 /* SPDX-License-Identifier: MIT */
19 * @extra_args == Operation-specific extra arguments (NULL if none).
28 /* x86/64 hypervisor: Syscall by 64-bit guest app ('64-on-64-on-64'). */
42 * - 32-bit hypervisor: with the supervisor_mode_kernel feature enabled
43 * - 64-bit hypervisor: 32-bit guest applications on Intel CPUs
44 * ('32-on-32-on-64', '32-on-64-on-64')
45 * [nb. also 64-bit guest applications on Intel CPUs
46 * ('64-on-64-on-64'), but syscall is preferred]
51 * x86/64 hypervisor: Syscall by 32-bit guest app on AMD CPUs
52 * ('32-on-32-on-64', '32-on-64-on-64')
[all …]
/linux-6.12.1/drivers/net/can/flexcan/
Dflexcan.h1 /* SPDX-License-Identifier: GPL-2.0
2 * flexcan.c - FLEXCAN CAN controller driver
4 * Copyright (c) 2005-2006 Varma Electronics Oy
6 * Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
10 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
17 #include <linux/can/rx-offload.h>
22 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece- FD Mode MB
25 * MX25 FlexCAN2 03.00.00.00 no no no no no no 64
26 * MX28 FlexCAN2 03.00.04.00 yes yes no no no no 64
27 * MX35 FlexCAN2 03.00.00.00 no no no no no no 64
[all …]
/linux-6.12.1/arch/x86/kvm/vmx/
Dvmx_ops.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 * for 64-bit targets. Preserving all registers allows the VMREAD inline asm
29 * 64-bit targets.
37 * exists primarily to enable instrumentation for the VM-Fail path.
46 "16-bit accessor invalid for 64-bit field"); in vmcs_check16()
48 "16-bit accessor invalid for 64-bit high field"); in vmcs_check16()
50 "16-bit accessor invalid for 32-bit field"); in vmcs_check16()
52 "16-bit accessor invalid for natural width field"); in vmcs_check16()
58 "32-bit accessor invalid for 16-bit field"); in vmcs_check32()
60 "32-bit accessor invalid for 64-bit field"); in vmcs_check32()
[all …]
/linux-6.12.1/arch/mips/include/asm/
Dmips-cm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
21 /* The base address of the CM L2-only sync region */
25 * mips_cm_phys_base - retrieve the physical base address of the CM
36 * mips_cm_l2sync_phys_base - retrieve the physical base address of the CM
37 * L2-sync region
40 * L2-cache only region. It provides a default implementation which reads the
49 * mips_cm_is64 - determine CM register width
52 * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
53 * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
[all …]
/linux-6.12.1/Documentation/arch/arm64/
Dasymmetric-32bit.rst2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
10 Date: 2021-05-17
16 of the CPUs are capable of executing 32-bit user applications. On such
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
20 ``-ENOEXEC``. If the mismatch is detected during late onlining of a
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
25 running legacy 32-bit binaries. Unsurprisingly, that doesn't work very
28 It seems inevitable that future SoCs will drop 32-bit support
[all …]
/linux-6.12.1/arch/mips/include/asm/octeon/
Dcvmx-fau.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
57 * bit will be set. Otherwise the value of the register before
67 * bit will be set. Otherwise the value of the register before
77 * bit will be set. Otherwise the value of the register before
87 * bit will be set. Otherwise the value of the register before
97 * the error bit will be set. Otherwise the value of the
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
[all …]
/linux-6.12.1/arch/mips/kernel/
Dunaligned.c18 * only the performance is affected. Much worse is that such code is non-
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
92 #include <asm/unaligned-emul.h>
97 #include "access-helper.h"
121 orig31 = regs->regs[31]; in emulate_load_store_insn()
133 * can assume therefore that the code is MIPS-aware and in emulate_load_store_insn()
177 regs->regs[insn.mxu_lx_format.rd] = value; in emulate_load_store_insn()
186 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
195 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
[all …]
/linux-6.12.1/arch/riscv/crypto/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 depends on 64BIT && RISCV_ISA_V && TOOLCHAIN_HAS_VECTOR_CRYPTO
13 Length-preserving ciphers: AES with ECB, CBC, CTS, CTR, XTS
16 - Zvkned vector crypto extension
17 - Zvbb vector extension (XTS)
18 - Zvkb vector crypto extension (CTR)
19 - Zvkg vector crypto extension (XTS)
23 depends on 64BIT && RISCV_ISA_V && TOOLCHAIN_HAS_VECTOR_CRYPTO
27 Length-preserving ciphers: ChaCha20 stream cipher algorithm
30 - Zvkb vector crypto extension
[all …]
/linux-6.12.1/arch/s390/crypto/
Dcrc32be-vx.c1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of CRC-32 checksums.
8 * This CRC-32 implementation algorithm processes the most-significant
9 * bit first (BE).
17 #include "crc32-vx.h"
19 /* Vector register range containing CRC-32 constants */
28 * The CRC-32 constant block contains reduction constants to fold and
31 * For the CRC-32 variants, the constants are precomputed according to
34 * R1 = x4*128+64 mod P(x)
[all …]
/linux-6.12.1/drivers/infiniband/hw/bnxt_re/
Dqplib_sp.h2 * Broadcom NetXtreme-E RoCE driver.
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
43 #include <rdma/bnxt_re-abi.h>
131 #define BNXT_QPLIB_ACCESS_LOCAL_WRITE BIT(0)
132 #define BNXT_QPLIB_ACCESS_REMOTE_READ BIT(1)
133 #define BNXT_QPLIB_ACCESS_REMOTE_WRITE BIT(2)
134 #define BNXT_QPLIB_ACCESS_REMOTE_ATOMIC BIT(3)
135 #define BNXT_QPLIB_ACCESS_MW_BIND BIT(4)
136 #define BNXT_QPLIB_ACCESS_ZERO_BASED BIT(5)
137 #define BNXT_QPLIB_ACCESS_ON_DEMAND BIT(6)
[all …]

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