cavium/liquidio/cn23xx_vf_regs.h

7  * Copyright (c) 2003-2016 Cavium, Inc.
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
47 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
52 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
55 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
58 /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
61 /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
64 /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data &
69 /*------- Request Queue Macros ---------*/
85 /*------------------ Masks ----------------*/
87 #define    CN23XX_PKT_INPUT_CTL_MAC_NUM                 BIT(29)
92 #define    CN23XX_PKT_INPUT_CTL_IS_64B                  BIT(24)
93 #define    CN23XX_PKT_INPUT_CTL_RST                     BIT(23)
94 #define    CN23XX_PKT_INPUT_CTL_QUIET                   BIT(28)
95 #define    CN23XX_PKT_INPUT_CTL_RING_ENB                BIT(22)
96 #define    CN23XX_PKT_INPUT_CTL_DATA_NS                 BIT(8)
97 #define    CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP        BIT(6)
98 #define    CN23XX_PKT_INPUT_CTL_DATA_RO                 BIT(5)
99 #define    CN23XX_PKT_INPUT_CTL_USE_CSR                 BIT(4)
100 #define    CN23XX_PKT_INPUT_CTL_GATHER_NS               BIT(3)
138 /* 64 registers for Output queue control - SLI_PKT(0..63)_OUTPUT_CONTROL */
141 /* 64 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */
144 /* 64 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */
147 /* 64 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */
150 /* 64 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */
153 /* 64 registers for Output Queue Packet Count - SLI_PKT0_CNTS */
156 /* 64 registers for Output Queue INT Levels - SLI_PKT0_INT_LEVELS */
159 /* Each Output Queue register is at a 16-byte Offset in BAR0 */
162 /*------- Output Queue Macros ---------*/
193 /*------------------ Masks ----------------*/
194 #define    CN23XX_PKT_OUTPUT_CTL_TENB                  BIT(13)
195 #define    CN23XX_PKT_OUTPUT_CTL_CENB                  BIT(12)
196 #define    CN23XX_PKT_OUTPUT_CTL_IPTR                  BIT(11)
197 #define    CN23XX_PKT_OUTPUT_CTL_ES                    BIT(9)
198 #define    CN23XX_PKT_OUTPUT_CTL_NSR                   BIT(8)
199 #define    CN23XX_PKT_OUTPUT_CTL_ROR                   BIT(7)
200 #define    CN23XX_PKT_OUTPUT_CTL_DPTR                  BIT(6)
201 #define    CN23XX_PKT_OUTPUT_CTL_BMODE                 BIT(5)
202 #define    CN23XX_PKT_OUTPUT_CTL_ES_P                  BIT(3)
203 #define    CN23XX_PKT_OUTPUT_CTL_NSR_P                 BIT(2)
204 #define    CN23XX_PKT_OUTPUT_CTL_ROR_P                 BIT(1)
205 #define    CN23XX_PKT_OUTPUT_CTL_RING_ENB              BIT(0)
229 /*------------------ Interrupt Masks ----------------*/
237 #define    CN23XX_INTR_MBOX_ENB                 BIT(0)