include/asm/mips-cm.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
21 /* The base address of the CM L2-only sync region */
25  * mips_cm_phys_base - retrieve the physical base address of the CM
36  * mips_cm_l2sync_phys_base - retrieve the physical base address of the CM
37  *                            L2-sync region
40  * L2-cache only region. It provides a default implementation which reads the
49  * mips_cm_is64 - determine CM register width
52  * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
53  * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
54  * or vice-versa. This variable indicates the width of the memory accesses
58  * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
63  * mips_cm_error_report - Report CM cache errors
72  * mips_cm_probe - probe for a Coherence Manager
75  * is successfully detected, else -errno.
82 	return -ENODEV;  in mips_cm_probe()
87  * mips_cm_present - determine whether a Coherence Manager is present
101  * mips_cm_has_l2sync - determine whether an L2-only sync region is present
103  * Returns true if the system implements an L2-only sync region, else false.
123 /* Size of the L2-only sync region */
142 /* GCR_CONFIG - Information about the system */
143 GCR_ACCESSOR_RO(64, 0x000, config)
150 /* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
151 GCR_ACCESSOR_RW(64, 0x008, base)
159 /* GCR_ACCESS - Controls core/IOCU access to GCRs */
163 /* GCR_REV - Indicates the Coherence Manager revision */
177 /* GCR_ERR_CONTROL - Control error checking logic */
179 #define CM_GCR_ERR_CONTROL_L2_ECC_EN		BIT(1)
180 #define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT	BIT(0)
182 /* GCR_ERR_MASK - Control which errors are reported as interrupts */
183 GCR_ACCESSOR_RW(64, 0x040, error_mask)
185 /* GCR_ERR_CAUSE - Indicates the type of error that occurred */
186 GCR_ACCESSOR_RW(64, 0x048, error_cause)
191 /* GCR_ERR_ADDR - Indicates the address associated with an error */
192 GCR_ACCESSOR_RW(64, 0x050, error_addr)
194 /* GCR_ERR_MULT - Indicates when multiple errors have occurred */
195 GCR_ACCESSOR_RW(64, 0x058, error_mult)
198 /* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
199 GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
201 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN		BIT(0)
203 /* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
204 GCR_ACCESSOR_RW(64, 0x080, gic_base)
206 #define CM_GCR_GIC_BASE_GICEN			BIT(0)
208 /* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
209 GCR_ACCESSOR_RW(64, 0x088, cpc_base)
211 #define CM_GCR_CPC_BASE_CPCEN			BIT(0)
213 /* GCR_REGn_BASE - Base addresses of CM address regions */
214 GCR_ACCESSOR_RW(64, 0x090, reg0_base)
215 GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
216 GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
217 GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
220 /* GCR_REGn_MASK - Size & destination of CM address regions */
221 GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
222 GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
223 GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
224 GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
227 #define CM_GCR_REGn_MASK_CCAOVREN		BIT(4)
228 #define CM_GCR_REGn_MASK_DROPL2			BIT(2)
235 /* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
237 #define CM_GCR_GIC_STATUS_EX			BIT(0)
239 /* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
241 #define CM_GCR_CPC_STATUS_EX			BIT(0)
243 /* GCR_ACCESS - Controls core/IOCU access to GCRs */
247 /* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
249 #define CM_GCR_L2_CONFIG_BYPASS			BIT(20)
254 /* GCR_SYS_CONFIG2 - Further information about the system */
258 /* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
261 #define CM_GCR_L2_PFT_CONTROL_PFTEN		BIT(8)
264 /* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
266 #define CM_GCR_L2_PFT_CONTROL_B_CEN		BIT(8)
269 /* GCR_L2SM_COP - L2 cache op state machine control */
271 #define CM_GCR_L2SM_COP_PRESENT			BIT(31)
278 #define CM_GCR_L2SM_COP_RUNNING			BIT(5)
291 /* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
292 GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
296 /* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
297 GCR_ACCESSOR_RW(64, 0x680, bev_base)
299 /* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
302 /* GCR_Cx_COHERENCE - Controls core coherence */
305 #define CM3_GCR_Cx_COHERENCE_COHEN		BIT(0)
307 /* GCR_Cx_CONFIG - Information about a core's configuration */
312 /* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
315 #define CM_GCR_Cx_OTHER_CLUSTER_EN		BIT(31)		/* CM >= 3.5 */
316 #define CM_GCR_Cx_OTHER_GIC_EN			BIT(30)		/* CM >= 3.5 */
327 /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
330 #define CM_GCR_Cx_RESET_BASE_MODE		BIT(1)
332 /* GCR_Cx_ID - Identify the current core */
337 /* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
339 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET	BIT(31)
340 #define CM_GCR_Cx_RESET_EXT_BASE_UEB		BIT(30)
343 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT	BIT(0)
346  * mips_cm_l2sync - perform an L2-only sync operation
348  * If an L2-only sync region is present in the system then this function
349  * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
354 		return -ENODEV;  in mips_cm_l2sync()
361  * mips_cm_revision() - return CM revision
375  * mips_cm_max_vp_width() - return the width in bits of VP indices
404  * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
424  * mips_cm_lock_other - lock access to redirect/other region
437  * mips_cm_unlock_other() calls cannot be pre-empted by anything which may
445  * mips_cm_unlock_other - unlock access to redirect/other region
461  * mips_cm_lock_other_cpu - lock access to redirect/other region