Lines Matching +full:64 +full:- +full:bit
7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
74 /* 2 scatch registers (64-bit) */
80 /* 1 registers (64-bit) - SLI_CTL_STATUS */
83 /* SLI Packet Input Jabber Register (64 bit register)
117 /* 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
122 /*1 register (64-bit) to determine whether IOQs are in reset. */
125 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
141 /* Starting bit of the TRS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
143 /* Starting bit of SRN field in CN23XX_SLI_PKT_MAC_RINFO64 register */
145 /* Starting bit of RPVF field in CN23XX_SLI_PKT_MAC_RINFO64 register */
147 /* Starting bit of NVFS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
152 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
155 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
158 /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
161 /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
164 /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data &
169 /*------- Request Queue Macros ---------*/
185 /*------------------ Masks ----------------*/
187 #define CN23XX_PKT_INPUT_CTL_MAC_NUM BIT(29)
192 #define CN23XX_PKT_INPUT_CTL_IS_64B BIT(24)
193 #define CN23XX_PKT_INPUT_CTL_RST BIT(23)
194 #define CN23XX_PKT_INPUT_CTL_QUIET BIT(28)
195 #define CN23XX_PKT_INPUT_CTL_RING_ENB BIT(22)
196 #define CN23XX_PKT_INPUT_CTL_DATA_NS BIT(8)
197 #define CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP BIT(6)
198 #define CN23XX_PKT_INPUT_CTL_DATA_RO BIT(5)
199 #define CN23XX_PKT_INPUT_CTL_USE_CSR BIT(4)
200 #define CN23XX_PKT_INPUT_CTL_GATHER_NS BIT(3)
238 /* 64 registers for Output queue control - SLI_PKT(0..63)_OUTPUT_CONTROL */
241 /* 64 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */
244 /* 64 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */
247 /* 64 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */
250 /* 64 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */
253 /* 64 registers for Output Queue Packet Count - SLI_PKT0_CNTS */
256 /* 64 registers for Output Queue INT Levels - SLI_PKT0_INT_LEVELS */
259 /* Each Output Queue register is at a 16-byte Offset in BAR0 */
262 /* 1 (64-bit register) for Output Queue backpressure across all rings. */
280 /*------- Output Queue Macros ---------*/
313 /*------------------ Masks ----------------*/
314 #define CN23XX_PKT_OUTPUT_CTL_TENB BIT(13)
315 #define CN23XX_PKT_OUTPUT_CTL_CENB BIT(12)
316 #define CN23XX_PKT_OUTPUT_CTL_IPTR BIT(11)
317 #define CN23XX_PKT_OUTPUT_CTL_ES BIT(9)
318 #define CN23XX_PKT_OUTPUT_CTL_NSR BIT(8)
319 #define CN23XX_PKT_OUTPUT_CTL_ROR BIT(7)
320 #define CN23XX_PKT_OUTPUT_CTL_DPTR BIT(6)
321 #define CN23XX_PKT_OUTPUT_CTL_BMODE BIT(5)
322 #define CN23XX_PKT_OUTPUT_CTL_ES_P BIT(3)
323 #define CN23XX_PKT_OUTPUT_CTL_NSR_P BIT(2)
324 #define CN23XX_PKT_OUTPUT_CTL_ROR_P BIT(1)
325 #define CN23XX_PKT_OUTPUT_CTL_RING_ENB BIT(0)
350 /* 2 registers (64-bit) - DMA Count - 1 for each DMA counter 0/1. */
353 /* 2 registers (64-bit) - DMA Timer 0/1, contains DMA timer values */
357 /* 2 registers (64-bit) - DMA count & Time Interrupt threshold -
362 /* Each DMA register is at a 16-byte Offset in BAR0 */
365 /*---------- DMA Counter Macros ---------*/
401 /* 1 register (64-bit) for Interrupt Summary */
404 /* 4 registers (64-bit) for Interrupt Enable for each Port */
417 /* 1 register (64-bit) to indicate which Output Queue reached pkt threshold */
420 /* 1 register (64-bit) to indicate which Output Queue reached time threshold */
423 /*------------------ Interrupt Masks ----------------*/
431 #define CN23XX_INTR_MBOX_ENB BIT(0)
435 #define CN23XX_INTR_MIO_INT BIT(1)
439 #define CN23XX_INTR_PKT_COUNT BIT(4)
440 #define CN23XX_INTR_PKT_TIME BIT(5)
444 #define CN23XX_INTR_M0UPB0_ERR BIT(8)
445 #define CN23XX_INTR_M0UPWI_ERR BIT(9)
446 #define CN23XX_INTR_M0UNB0_ERR BIT(10)
447 #define CN23XX_INTR_M0UNWI_ERR BIT(11)
484 /* Sum of interrupts for all PCI-Express Data Interrupts */
508 /* 4 Registers (64 - bit) */
529 /* 1 register (64-bit) - provides DMA Enable */
532 /* 1 register (64-bit) - Controls the DMA IO Operation */
535 /* 1 register (64-bit) - Provides DMA Instr'n Queue Enable */
538 /* 1 register (64-bit) - DPI_REQ_ERR_RSP
539 * Indicates which Instr'n Queue received error response from the IO sub-system
543 /* 1 register (64-bit) - DPI_REQ_ERR_RST
548 /* 6 register (64-bit) - DPI_DMA_ENG(0..5)_EN
554 /* 8 register (64-bit) - DPI_DMA(0..7)_REQQ_CTL
561 /* 6 register (64-bit) - DPI_ENG(0..5)_BUF
568 /* 4 Registers (64-bit) */
580 #define CN23XX_DPI_DMA_O_ADD1 BIT(19)
581 /*selecting 64-bit Byte Swap Mode */
582 #define CN23XX_DPI_DMA_O_ES BIT(15)
583 #define CN23XX_DPI_DMA_O_MODE BIT(14)