Home
last modified time | relevance | path

Searched +full:4 +full:- +full:31 (Results 1 – 25 of 1062) sorted by relevance

12345678910>>...43

/linux-6.12.1/Documentation/userspace-api/media/v4l/
Dmetafmt-vsp1-hgo.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
[all …]
Dmetafmt-vsp1-hgt.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgt:
9 Renesas R-Car VSP1 2-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1
16 2-D Histogram (HGT) engine.
28 The Saturation position **n** (0 - 31) of the bucket in the matrix is
33 The Hue position **m** (0 - 5) of the bucket in the matrix depends on
43 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5
50 5U 0L 0U 1L 1U 2L 2U 3L 3U 4L 4U 5L 5U 0L
72 0L <= 0U <= 1L <= 1U <= 2L <= 2U <= 3L <= 3U <= 4L <= 4U <= 5L <= 5U
[all …]
/linux-6.12.1/arch/powerpc/xmon/
Dppc-opc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
27 inserting operands into instructions and vice-versa is kept in this
173 /* The BD field in a B form instruction when the - modifier is used.
179 /* The BD field in a B form instruction when the - modifier is used
224 /* The BO field in a B form instruction when the + or - modifier is
254 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
411 /* If the FXM4 operand is omitted, use the sentinel value -1. */
412 { -1, -1, NULL, NULL, 0},
[all …]
/linux-6.12.1/arch/powerpc/crypto/
Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
28 # setup r^4, r^3, r^2, r vectors
29 # vs [r^1, r^3, r^2, r^4]
56 #include <asm/asm-offsets.h>
[all …]
Dcurve25519-ppc64le_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 # [1] https://github.com/dot-asm/cryptogams/
11 # Copyright (c) 2006-2017, CRYPTOGAMS by <appro@openssl.org>
58 # - Added x25519_fe51_sqr_times, x25519_fe51_frombytes, x25519_fe51_tobytes
61 # Copyright 2024- IBM Corp.
63 # X25519 lower-level primitives for PPC64.
73 stdu 1,-144(1)
84 std 31,136(1)
87 ld 7,0(4)
88 ld 8,8(4)
[all …]
Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
17 # 4. c += d; b ^= c; b <<<= 7
24 # 4 blocks (a b c d)
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
81 stdu 1,-752(1)
100 SAVE_GPR 31, 248, 1
114 SAVE_VRS 31, 176, 9
133 SAVE_VSX 31, 464, 9
[all …]
/linux-6.12.1/arch/alpha/include/asm/
Dxor.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-alpha/xor.h
5 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
53 .align 4 \n\
60 ldq $4,16($17) \n\
78 xor $4,$5,$4 \n\
82 stq $4,16($17) \n\
108 .align 4 \n\
115 ldq $4,8($18) \n\
131 xor $3,$4,$4 # 6 cycles from $4 load \n\
[all …]
/linux-6.12.1/tools/arch/x86/kcpuid/
Dcpuid.csv1 # SPDX-License-Identifier: CC0-1.0
2 # Generator: x86-cpuid-db v1.0
5 # Auto-generated file.
6 # Please submit all updates and bugfixes to https://x86-cpuid.org
15 … 0, 0, eax, 31:0, max_std_leaf , Highest cpuid standard leaf supported
16 0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
17 0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
18 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7
24 1, 0, eax, 7:4, base_model , Base CPU model ID
32 1, 0, ebx, 31:24, local_apic_id , Initial local APIC physical ID
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtw89/
Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
14 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0)
15 #define DATA_RATE_HT_IDX_MASK_V1 GENMASK(4, 0)
17 #define DATA_RATE_HT_NSS_MASK GENMASK(4, 3)
18 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4)
21 #define DATA_RATE_MCS_MASK_V1 GENMASK(4, 0)
28 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
41 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs()
49 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_mcs()
62 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_nss()
[all …]
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt2712-apmixedsys.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include "clk-pll.h"
13 #include "clk-mtk.h"
15 #include <dt-bindings/clock/mt2712-clk.h>
57 { .div = 4, .freq = 157625000 },
66 { .div = 4, .freq = 157625000 },
75 { .div = 4, .freq = 125125000 },
81 HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
83 HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
85 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
[all …]
/linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt7603/
Dregs.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
19 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
30 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
44 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
51 #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
58 #define MT_WPDMA_DEBUG_IDX GENMASK(31, 28)
64 #define MT_TXTIME_THRESH(n) (MT_TXTIME_THRESH_BASE + ((n) * 4))
67 #define MT_PAGE_COUNT(n) (MT_PAGE_COUNT_BASE + ((n) * 4))
[all …]
/linux-6.12.1/arch/alpha/lib/
Dmemset.S1 /* SPDX-License-Identifier: GPL-2.0 */
10 * This routine is "moral-ware": you are free to use it any way you wish, and
35 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
36 sll $17,16,$1 /* E1 (p-c latency, next cycle) */
38 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
39 sll $17,32,$1 /* E1 (p-c latency, next cycle) */
40 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
41 ldq_u $31,0($30) /* .. E1 */
51 beq $1,within_one_quad /* .. E1 (note EV5 zero-latency forwarding) */
53 beq $3,aligned /* .. E1 (note EV5 zero-latency forwarding) */
[all …]
Dclear_user.S1 /* SPDX-License-Identifier: GPL-2.0 */
8 * We have to make sure that $0 is always up-to-date and contains the
19 .long 99b - .; \
20 lda $31, $exception-99b($31); \
25 .align 4
33 and $1, 3, $4 # e0 :
34 beq $4, 1f # .. e1 :
36 0: EX( stq_u $31, 0($16) ) # e0 : zero one word
38 subq $4, 1, $4 # e0 :
40 bne $4, 0b # e1 :
[all …]
/linux-6.12.1/arch/arm64/tools/
Dsysreg1 # SPDX-License-Identifier: GPL-2.0-only
44 # NI - Not implemented
45 # IMP - Implemented
53 Field 31:0 DTRRX
57 Res0 63:31
69 Field 31 TFO
93 Field 31:0 DTRTX
98 Field 31:0 EDECCR
101 Sysreg OSLAR_EL1 2 0 1 0 4
108 UnsignedEnum 31:28 RAS
[all …]
/linux-6.12.1/drivers/clk/sunxi-ng/
Dccu-sun9i-a80.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
26 * The CPU PLLs are actually NP clocks, with P being /1 or /4. However
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
36 .enable = BIT(31),
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
50 .enable = BIT(31),
57 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
[all …]
Dccu-sun6i-a31.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
30 #include "ccu-sun6i-a31.h"
32 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
35 4, 2, /* K */
37 BIT(31), /* gate */
42 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
[all …]
/linux-6.12.1/arch/arm/crypto/
Dsha1-armv4-large.S2 @ SPDX-License-Identifier: GPL-2.0
23 @ Size/performance trade-off
28 @ armv4-small 392/+29% 1958/+64% 2250/+96%
29 @ armv4-compact 740/+89% 1552/+26% 1840/+22%
30 @ armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
31 @ full unroll ~5100/+260% ~1260/+4% ~1300/+5%
42 @ i-cache availability, branch penalties, etc.
49 @ [***] which is also ~35% better than compiler generated code. Dual-
55 @ Rescheduling for dual-issue pipeline resulted in 13% improvement on
61 @ Profiler-assisted and platform-specific optimization resulted in 10%
[all …]
/linux-6.12.1/drivers/net/wireless/mediatek/mt76/
Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
46 #define MT_TX_FREE_PAIR BIT(31)
50 #define MT_TXD0_Q_IDX GENMASK(31, 25)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
67 #define MT_TXD2_FIX_RATE BIT(31)
80 #define MT_TXD2_FRAME_TYPE GENMASK(5, 4)
83 #define MT_TXD3_SN_VALID BIT(31)
91 #define MT_TXD3_DAS BIT(4)
97 #define MT_TXD4_PN_LOW GENMASK(31, 0)
99 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
[all …]
Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
26 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
32 #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
51 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
69 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
83 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
97 #define MT_RXD10_QOS_CTL GENMASK(31, 16)
99 #define MT_RXD11_HT_CONTROL GENMASK(31, 0)
101 /* P-RXV */
103 #define MT_PRXV_TX_DCM BIT(4)
[all …]
/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_guc_fwif.h1 /* SPDX-License-Identifier: MIT */
13 #define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 4
26 #define GUC_CLIENT_PRIORITY_NUM 4
32 #define GUC_VIDEO_ENGINE2 4
39 #define GUC_COMPUTE_CLASS 4
61 /* 32-bit KLV structure as used by policy updates and others */
78 /* GUC_CTL_* - Parameters for loading the GuC */
84 #define GUC_LOG_CRASH_SHIFT 4
117 #define GUC_LOG_DESTINATION_MASK (3 << 4)
121 #define GUC_CTL_ADS 4
[all …]
/linux-6.12.1/drivers/bus/mhi/
Dcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
68 #define BHI_STATUS_MASK GENMASK(31, 30)
91 #define BHIE_TXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
100 #define BHIE_RXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
107 #define MHICFG_NHWER_MASK GENMASK(31, 24)
126 #define MHI_TRE_CMD_RESET_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
133 #define MHI_TRE_CMD_STOP_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
140 #define MHI_TRE_CMD_START_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
144 #define MHI_TRE_GET_DWORD(tre, word) le32_to_cpu((tre)->dword[(word)])
145 #define MHI_TRE_GET_CMD_CHID(tre) FIELD_GET(GENMASK(31, 24), MHI_TRE_GET_DWORD(tre, 1))
[all …]
/linux-6.12.1/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
Dhw_atl2_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
82 /* rx rpf_rss_red1_data_[4:0] bitfield definitions
83 * preprocessor definitions for the bitfield "rpf_rss_red1_data[4:0]".
84 * port="pif_rpf_rss_red1_data_i[4:0]"
87 /* register address for bitfield rpf_rss_red1_data[4:0] */
89 (0x100 * !!((TC) > 3)) + (INDEX) * 4)
90 /* bitmask for bitfield rpf_rss_red1_data[4:0] */
91 #define HW_ATL2_RPF_RSS_REDIR_MSK(TC) (0x00000001F << (5 * ((TC) % 4)))
92 /* lower bit position of bitfield rpf_rss_red1_data[4:0] */
93 #define HW_ATL2_RPF_RSS_REDIR_SHIFT(TC) (5 * ((TC) % 4))
[all …]
/linux-6.12.1/drivers/net/ipa/reg/
Dipa_reg-v4.2.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
17 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
31 /* Bits 21-31 reserved */
41 [RAM_ARB] = BIT(4),
67 /* Bits 30-31 reserved */
78 /* Bits 22-23 reserved */
80 /* Bits 25-31 reserved */
87 [MEM_BADDR] = GENMASK(31, 16),
94 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
[all …]
Dipa_reg-v3.5.1.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
17 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
18 /* Bits 5-31 reserved */
28 [RAM_ARB] = BIT(4),
46 /* Bits 22-31 reserved */
57 /* Bits 22-23 reserved */
59 /* Bits 25-31 reserved */
66 [MEM_BADDR] = GENMASK(31, 16),
73 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
[all …]
/linux-6.12.1/arch/parisc/math-emu/
Dfloat.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
26 PA header file -- do not include this header file for non-PA builds.
41 * floating-point precisions.
44 * +-------+-------+-------+-------+-------+-------+-------+-------+
46 * +-------+-------+-------+-------+-------+-------+-------+-------+
56 #define Sexponentmantissa(object) Bitfield_mask( 1, 31,object)
61 #define Shiddenhigh3mantissa(object) Bitfield_extract( 8, 4,object)
[all …]

12345678910>>...43