realtek/rtw89/txrx.h

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
14 #define DATA_RATE_HT_IDX_MASK		GENMASK(4, 0)
15 #define DATA_RATE_HT_IDX_MASK_V1	GENMASK(4, 0)
17 #define DATA_RATE_HT_NSS_MASK		GENMASK(4, 3)
18 #define DATA_RATE_VHT_HE_NSS_MASK	GENMASK(6, 4)
21 #define DATA_RATE_MCS_MASK_V1		GENMASK(4, 0)
28 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_rate_mode()
41 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_ht_mcs()
49 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_mcs()
62 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_nss()
69 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)
82 #define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
83 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16)
84 #define RTW89_TXWD_BODY1_SEC_KEYID GENMASK(5, 4)
98 /* TX WD BODY DWORD 4 */
99 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)
103 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)
111 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31)
126 #define RTW89_TXWD_INFO0_MULTIPORT_ID GENMASK(6, 4)
142 /* TX WD INFO DWORD 4 */
144 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31)
150 #define BE_TXD_BODY0_HW_SSN_SEL GENMASK(4, 2)
166 #define BE_TXD_BODY0_HCI_SEQNUM_MODE BIT(31)
176 #define BE_TXD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
185 #define BE_TXD_BODY2_MACID GENMASK(31, 24)
198 #define BE_TXD_BODY3_BAND1_SU_RTY_V1 BIT(31)
200 /* TX WD BODY DWORD 4 */
203 #define BE_TXD_BODY4_SEC_IV_L1 GENMASK(31, 24)
209 #define BE_TXD_BODY5_SEC_IV_H5 GENMASK(31, 24)
212 #define BE_TXD_BODY6_MU_TC GENMASK(4, 0)
221 #define BE_TXD_BODY6_RU_POS GENMASK(31, 24)
232 #define BE_TXD_BODY7_USERATE_SEL BIT(31)
236 #define BE_TXD_INFO0_MULTIPORT_ID GENMASK(6, 4)
245 #define BE_TXD_INFO0_ACK_CH_INFO BIT(31)
255 #define BE_TXD_INFO1_SW_DEFINE GENMASK(31, 28)
266 #define BE_TXD_INFO2_SIFS_TX_V1 BIT(31)
270 #define BE_TXD_INFO3_SPE_PKT_TYPE GENMASK(7, 4)
283 #define BE_TXD_INFO3_FORCE_BSS_CLR BIT(31)
285 /* TX WD INFO DWORD 4 */
294 #define BE_TXD_INFO4_HW_RTS_EN BIT(31)
297 #define BE_TXD_INFO5_SR_RATE_V1 GENMASK(4, 0)
299 #define BE_TXD_INFO5_NDPA_DURATION GENMASK(31, 16)
307 #define BE_TXD_INFO6_UL_RF_GAIN_IDX GENMASK(31, 22)
321 #define BE_TXD_INFO7_EXTEND_MODE_SEL GENMASK(31, 28)
331 #define AX_RXD_LONG_RXD BIT(31)
335 #define AX_RXD_PPDU_CNT_MASK GENMASK(6, 4)
345 #define AX_RXD_BW_MASK GENMASK(31, 30)
346 #define AX_RXD_BW_v1_MASK GENMASK(31, 29)
349 #define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
356 #define AX_RXD_AMPDU_END_PKT BIT(4)
377 #define AX_RXD_MD BIT(4)
386 #define AX_RXD_FRAG_MASK GENMASK(31, 28)
398 #define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0)
417 #define RTW89_RXINFO_USER_BCN BIT(4)
427 #define RTW89_RXINFO_W0_USR_NUM_V1 GENMASK(4, 0)
434 #define RTW89_RXINFO_W0_LONG_RXD GENMASK(31, 30)
443 #define RTW89_PHY_STS_HDR_W0_IE_MAP GENMASK(4, 0)
447 #define RTW89_PHY_STS_HDR_W0_RSSI_AVG GENMASK(31, 24)
451 #define RTW89_PHY_STS_HDR_W1_RSSI_D GENMASK(31, 24)
464 #define RTW89_PHY_STS_IEHDR_TYPE GENMASK(4, 0)
475 #define BE_RXD_LONG_RXD BIT(31)
491 #define BE_RXD_TID_MASK GENMASK(31, 28)
495 #define BE_RXD_BIP_KEYID BIT(4)
516 #define BE_RXD_GET_CH_INFO_V1_MASK GENMASK(31, 30)
524 #define BE_RXD_RX_DATARATE_MASK GENMASK(31, 20)
527 #define BE_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
537 #define BE_RXD_SEC_CAM_IDX_MASK GENMASK(31, 24)
540 #define BE_RXD_PATTERN_IDX_MASK GENMASK(4, 0)
556 #define BE_RXD_MAC_ADDR_MASK GENMASK(31, 0)
599 #define RTW89_PHY_STS_IE01_W0_RX_PATH_EN GENMASK(31, 28)
601 #define RTW89_PHY_STS_IE01_W1_PREMB_CFO GENMASK(31, 20)
621 #define RTW89_PHY_STS_IE01_V2_W5_BW_IDX GENMASK(31, 29)
622 #define RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A GENMASK(11, 4)
624 #define RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C GENMASK(11, 4)
632 	RTW89_TXCH_ACH4	= 4,
644 	RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1
653 	RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1
703 	case 4:  in rtw89_core_get_qsel()
750 	case 4:  in rtw89_core_get_tid_indicate()