Lines Matching +full:4 +full:- +full:31
1 /* SPDX-License-Identifier: ISC */
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
19 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
30 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
44 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
51 #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
58 #define MT_WPDMA_DEBUG_IDX GENMASK(31, 28)
64 #define MT_TXTIME_THRESH(n) (MT_TXTIME_THRESH_BASE + ((n) * 4))
67 #define MT_PAGE_COUNT(n) (MT_PAGE_COUNT_BASE + ((n) * 4))
74 #define MT_SCH_4_FORCE_QID GENMASK(4, 0)
79 #define MT_GROUP_THRESH(n) (MT_GROUP_THRESH_BASE + ((n) * 4))
125 #define MT_PSE_RTA_QUEUE_ID GENMASK(4, 0)
130 #define MT_PSE_RTA_BUSY BIT(31)
137 #define MT_AGC(n) (MT_AGC_BASE + ((n) * 4))
140 #define MT_AGC1(n) (MT_AGC1_BASE + ((n) * 4))
146 #define MT_RXTD(n) (MT_RXTD_BASE + ((n) * 4))
148 #define MT_RXTD_6_ACI_TH GENMASK(4, 0)
158 ((n) * 4))
161 #define MT_PHYCTRL(n) (MT_PHYCTRL_BASE + ((n) * 4))
167 #define MT_PHYCTRL_STAT_PD_OFDM GENMASK(31, 16)
171 #define MT_PHYCTRL_STAT_MDRDY_OFDM GENMASK(31, 16)
189 #define MT_AGG_ARxCR_LIMIT_SHIFT(_n) (4 * (_n))
196 #define MT_AGG_LIMIT_AC(_n) GENMASK(((_n) + 1) * 8 - 1, (_n) * 8)
213 #define MT_AGG_PCR_RTS_PKT_THR GENMASK(31, 25)
222 #define MT_AGG_CONTROL_CFEND_RATE GENMASK(15, 4)
224 #define MT_AGG_CONTROL_BAR_RATE GENMASK(31, 20)
253 #define MT_DMA_FQCR0_BUSY BIT(31)
272 #define MT_WMM_AIFSN_SHIFT(_n) ((_n) * 4)
285 #define MT_WF_ARB_RQCR_RXV_START BIT(4)
297 #define MT_ARB_SCR_TBTT_BCAST_PRIO BIT(31)
327 #define MT_WF_ARB_BCN_START_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
331 #define MT_WF_ARB_BCN_FLUSH_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
335 #define MT_WF_ARB_CAB_START_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
339 #define MT_WF_ARB_CAB_FLUSH_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
341 #define MT_WF_ARB_CAB_COUNT(n) MT_WF_ARB(0x128 + (n) * 4)
342 #define MT_WF_ARB_CAB_COUNT_SHIFT 4
345 ((n) > 4 ? 1 : 0)))
346 #define MT_WF_ARB_CAB_COUNT_B0_SHIFT(n) (((n) > 12 ? (n) - 12 : \
347 ((n) > 4 ? (n) - 4 : \
348 (n) ? (n) + 3 : 0)) * 4)
375 #define MT_TMAC_TCR_SMOOTHING BIT(31)
386 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
389 #define MT_TXREQ_CCA_SRC_SEL GENMASK(31, 30)
416 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4)
454 #define MT_WF_RMACDR_TSF_TIM BIT(4)
475 #define MT_WF_CFG_OFF_WOCCR_TMAC_GC_DIS BIT(4)
505 #define MT_LPON_BTEIR_MBSS_MODE GENMASK(31, 29)
516 #define MT_TBTT_CAL_ENABLE BIT(31)
531 #define MT_HW_INT3_PRE_TBTT0 BIT(31)
543 #define MT_WTBL_RIUCR1_RATE2_LO GENMASK(31, 24)
547 #define MT_WTBL_RIUCR2_RATE3 GENMASK(15, 4)
549 #define MT_WTBL_RIUCR2_RATE5_LO GENMASK(31, 28)
554 #define MT_WTBL_RIUCR3_RATE7 GENMASK(31, 20)
563 #define MT_MIB_CTL_READ_CLR_DIS BIT(31)
565 #define MT_MIB_STAT(_n) MT_MIB(0x08 + (_n) * 4)
581 #define MT_TX_HW_QUEUE_MGMT 4
600 #define MT_LED_STATUS_OFF GENMASK(31, 24)
629 #define MT_EFUSE_CTRL_SEL BIT(31)
631 #define MT_EFUSE_WDATA(_i) (0x010 + ((_i) * 4))
632 #define MT_EFUSE_RDATA(_i) (0x030 + ((_i) * 4))
641 #define MT_WTBL1_SIZE (8 * 4)
642 #define MT_WTBL2_SIZE (16 * 4)
644 #define MT_WTBL3_SIZE (16 * 4)
647 #define MT_WTBL4_SIZE (8 * 4)
659 #define MT_WTBL1_W0_WRITE_BURST BIT(31)
661 #define MT_WTBL1_W1_ADDR_LO GENMASK(31, 0)
687 #define MT_WTBL1_W2_GROUP_ID BIT(31)
696 #define MT_WTBL1_W3_SKIP_TX BIT(31)
701 #define MT_WTBL1_W4_PARTIAL_AID GENMASK(31, 23)
703 #define MT_WTBL2_W0_PN_LO GENMASK(31, 0)
710 #define MT_WTBL2_W2_TID2_SN_LO GENMASK(31, 24)
713 #define MT_WTBL2_W3_TID3_SN GENMASK(15, 4)
715 #define MT_WTBL2_W3_TID5_SN_LO GENMASK(31, 28)
719 #define MT_WTBL2_W4_TID7_SN GENMASK(31, 20)
722 #define MT_WTBL2_W5_FAIL_COUNT_RATE1 GENAMSK(31, 16)
727 #define MT_WTBL2_W6_TX_COUNT_RATE5 GENMASK(31, 24)
730 #define MT_WTBL2_W7_FAIL_COUNT_CUR_BW GENMASK(31, 16)
733 #define MT_WTBL2_W8_FAIL_COUNT_OTHER_BW GENMASK(31, 16)
735 #define MT_WTBL2_W9_POWER_OFFSET GENMASK(4, 0)
747 #define MT_WTBL2_W9_RATE_IDX GENMASK(31, 29)
751 #define MT_WTBL2_W10_RATE3_LO GENMASK(31, 24)
754 #define MT_WTBL2_W11_RATE4 GENMASK(15, 4)
756 #define MT_WTBL2_W11_RATE6_LO GENMASK(31, 28)
760 #define MT_WTBL2_W12_RATE8 GENMASK(31, 20)
771 #define MT_WTBL2_W14_ANT_SEL GENMASK(31, 26)
775 #define MT_WTBL2_W15_BA_EN_TIDS GENMASK(31, 24)
778 #define MT_WTBL1_OR_PSM_WRITE BIT(31)