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/linux-6.12.1/arch/parisc/include/asm/
Delf.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */
29 #define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */
30 #define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */
60 #define R_PARISC_DIR32 1 /* Direct 32-bit reference. */
61 #define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */
62 #define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */
63 #define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */
64 #define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */
65 #define R_PARISC_PCREL32 9 /* 32-bit rel. address. */
[all …]
/linux-6.12.1/Documentation/filesystems/ext4/
Dgroup_descr.rst1 .. SPDX-License-Identifier: GPL-2.0
4 -----------------------
38 checksum is the lower 16 bits of the checksum of the FS UUID, the group
45 .. list-table::
47 :header-rows: 1
49 * - Offset
50 - Size
51 - Name
52 - Description
53 * - 0x0
[all …]
/linux-6.12.1/arch/sparc/include/asm/
Dpcic.h1 /* SPDX-License-Identifier: GPL-2.0 */
47 #define PCI_SPACE_SIZE 0x1000000 /* 16 MB */
50 #define PCI_DIAGNOSTIC_0 0x40 /* 32 bits */
51 #define PCI_SIZE_0 0x44 /* 32 bits */
52 #define PCI_SIZE_1 0x48 /* 32 bits */
53 #define PCI_SIZE_2 0x4c /* 32 bits */
54 #define PCI_SIZE_3 0x50 /* 32 bits */
55 #define PCI_SIZE_4 0x54 /* 32 bits */
56 #define PCI_SIZE_5 0x58 /* 32 bits */
57 #define PCI_PIO_CONTROL 0x60 /* 8 bits */
[all …]
/linux-6.12.1/drivers/net/ipa/reg/
Dipa_reg-v4.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
6 #include <linux/bits.h>
29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
32 /* Bits 22-31 reserved */
54 [H_DCPH] = BIT(16),
78 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
80 /* Bits 22-23 reserved */
82 /* Bits 25-31 reserved */
89 [MEM_BADDR] = GENMASK(31, 16),
[all …]
Dipa_reg-v5.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
6 #include <linux/bits.h>
15 [MAX_PROD_PIPES] = GENMASK(23, 16),
38 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
39 /* Bits 17-18 reserved */
44 /* Bits 28-29 reserved */
68 [H_DCPH] = BIT(16),
91 [ROUTE_DEF_HDR_OFST] = GENMASK(25, 16),
95 /* Bits 29-31 reserved */
[all …]
Dipa_reg-v5.0.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
6 #include <linux/bits.h>
15 [MAX_PROD_PIPES] = GENMASK(23, 16),
38 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
45 /* Bits 28-29 reserved */
69 [H_DCPH] = BIT(16),
92 [ROUTE_DEF_HDR_OFST] = GENMASK(25, 16),
96 /* Bits 29-31 reserved */
103 [MEM_BADDR] = GENMASK(31, 16),
[all …]
Dipa_reg-v4.11.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
6 #include <linux/bits.h>
29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
36 /* Bits 24-29 reserved */
60 [H_DCPH] = BIT(16),
84 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
86 /* Bits 22-23 reserved */
88 /* Bits 25-31 reserved */
95 [MEM_BADDR] = GENMASK(31, 16),
[all …]
Dipa_reg-v4.7.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
6 #include <linux/bits.h>
29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
32 /* Bits 22-31 reserved */
54 [H_DCPH] = BIT(16),
78 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
80 /* Bits 22-23 reserved */
82 /* Bits 25-31 reserved */
89 [MEM_BADDR] = GENMASK(31, 16),
[all …]
Dipa_reg-v4.9.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
6 #include <linux/bits.h>
29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
35 /* Bits 25-29 reserved */
59 [H_DCPH] = BIT(16),
83 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
85 /* Bits 22-23 reserved */
87 /* Bits 25-31 reserved */
94 [MEM_BADDR] = GENMASK(31, 16),
[all …]
Dipa_reg-v4.2.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
6 #include <linux/bits.h>
29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
31 /* Bits 21-31 reserved */
53 [H_DCPH] = BIT(16),
67 /* Bits 30-31 reserved */
76 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
78 /* Bits 22-23 reserved */
80 /* Bits 25-31 reserved */
[all …]
Dipa_reg-v3.5.1.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
6 #include <linux/bits.h>
18 /* Bits 5-31 reserved */
40 [H_DCPH] = BIT(16),
46 /* Bits 22-31 reserved */
55 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
57 /* Bits 22-23 reserved */
59 /* Bits 25-31 reserved */
66 [MEM_BADDR] = GENMASK(31, 16),
[all …]
Dipa_reg-v3.1.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
6 #include <linux/bits.h>
18 /* Bits 5-31 reserved */
40 [H_DCPH] = BIT(16),
41 /* Bits 17-31 reserved */
50 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
52 /* Bits 22-23 reserved */
54 /* Bits 25-31 reserved */
61 [MEM_BADDR] = GENMASK(31, 16),
[all …]
/linux-6.12.1/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
Dphy_qmath.c1 // SPDX-License-Identifier: ISC
9 * Description: This function make 16 bit unsigned multiplication.
10 * To fit the output into 16 bits the 32 bit multiplication result is right
11 * shifted by 16 bits.
15 return (u16) (((u32) op1 * (u32) op2) >> 16); in qm_mulu16()
19 * Description: This function make 16 bit multiplication and return the result
20 * in 16 bits. To fit the multiplication result into 16 bits the multiplication
21 * result is right shifted by 15 bits. Right shifting 15 bits instead of 16 bits
23 * When both the 16bit inputs are 0x8000 then the output is saturated to
39 * result. If the result overflow 32 bits, the output will be saturated to
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Domap3-devkit8000-lcd-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "omap3-devkit8000-common.dtsi"
15 compatible = "panel-dpi";
18 enable-gpios = <&twl_gpio 18 GPIO_ACTIVE_HIGH>;
22 remote-endpoint = <&dpi_lcd_out>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 remote-endpoint = <&lcd_in>;
35 data-lines = <24>;
41 regulator-min-microvolt = <1800000>;
[all …]
/linux-6.12.1/drivers/pci/
Dpci-bridge-emul.c1 // SPDX-License-Identifier: GPL-2.0
21 #include "pci-bridge-emul.h"
28 * struct pci_bridge_reg_behavior - register bits behaviors
29 * @ro: Read-Only bits
30 * @rw: Read-Write bits
31 * @w1c: Write-1-to-Clear bits
33 * Reads and Writes will be filtered by specified behavior. All other bits not
36 * multi-bit fields) when read".
39 /* Read-only bits */
42 /* Read-write bits */
[all …]
/linux-6.12.1/Documentation/userspace-api/media/rc/
Drc-protos.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
22 Some remotes have a pointer-type device which can used to control the
29 rc-5 (RC_PROTO_RC5)
30 -------------------
32 This IR protocol uses manchester encoding to encode 14 bits. There is a
38 .. flat-table:: rc5 bits scancode mapping
41 * - rc-5 bit
43 - scancode bit
45 - description
47 * - 1
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx7d-pico-hobbit.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 #include "imx7d-pico.dtsi"
8 model = "TechNexion PICO-IMX7D Board using Hobbit baseboard";
9 compatible = "technexion,imx7d-pico-hobbit", "fsl,imx7d";
12 compatible = "gpio-leds";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_gpio_leds>;
17 label = "gpio-led";
23 compatible = "simple-audio-card";
24 simple-audio-card,name = "imx7-sgtl5000";
[all …]
/linux-6.12.1/arch/x86/crypto/
Dcrct10dif-pcl-asm_64.S2 # Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
50 # /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
68 movdqu \offset+16(buf), %xmm12
95 # Assumes len >= 16.
107 movdqu 16*0(buf), %xmm0
108 movdqu 16*1(buf), %xmm1
109 movdqu 16*2(buf), %xmm2
110 movdqu 16*3(buf), %xmm3
111 movdqu 16*4(buf), %xmm4
112 movdqu 16*5(buf), %xmm5
[all …]
/linux-6.12.1/drivers/ras/amd/atl/
Dreg_fields.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 * Rev Fieldname Bits
46 * Rev Fieldname Bits
69 * Rev Fieldname Bits
77 * DF4 DstFabricID [27:16]
80 * DF4p5 DstFabricID [23:16]
85 #define DF4_DST_FABRIC_ID GENMASK(27, 16)
86 #define DF4p5_DST_FABRIC_ID GENMASK(23, 16)
94 * Rev Fieldname Bits
100 * DF3 DieIdMask [18:16]
[all …]
/linux-6.12.1/drivers/mfd/
Ddb8500-prcmu-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) ST-Ericsson SA 2010
15 #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end)) macro
60 #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16)
83 #define PRCM_HOSTACCESS_REQ_WAKE_REQ BIT(16)
120 #define PRCM_PLL_FREQ_D_MASK BITS(0, 7)
122 #define PRCM_PLL_FREQ_N_MASK BITS(8, 13)
123 #define PRCM_PLL_FREQ_R_SHIFT 16
124 #define PRCM_PLL_FREQ_R_MASK BITS(16, 18)
143 #define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK BITS(0, 2)
[all …]
/linux-6.12.1/arch/arm/boot/dts/microchip/
Dat91sam9261ek.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9261ek.dts - Device Tree file for Atmel at91sam9261 reference board
5 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
7 /dts-v1/;
16 stdout-path = "serial0:115200n8";
25 clock-frequency = <32768>;
29 clock-frequency = <18432000>;
40 atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>;
44 bits-per-pixel = <16>;
45 atmel,lcdcon-backlight;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/media/i2c/
Dtda1997x.txt1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
[all …]
/linux-6.12.1/drivers/net/ethernet/emulex/benet/
Dbe_hw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
17 * it writes the register with hi=1 and the upper bits of the physical address
20 * bits in the address. It must poll the ready bit until the command is
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
90 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
109 #define SLI_INTF_HINT1_SHIFT 16
127 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
[all …]
/linux-6.12.1/drivers/crypto/hisilicon/sec2/
Dsec_crypto.h1 /* SPDX-License-Identifier: GPL-2.0 */
27 SEC_HMAC_CCM_MAC = 16,
28 SEC_HMAC_GCM_MAC = 16,
31 SEC_HMAC_MD5_MAC = 16,
97 * mac_len: 0~4 bits
98 * a_key_len: 5~10 bits
99 * a_alg: 11~16 bits
104 * c_icv_len: 0~5 bits
105 * c_width: 6~8 bits
106 * c_key_len: 9~11 bits
[all …]
/linux-6.12.1/arch/arm/crypto/
Dcrct10dif-ce-core.S2 // Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions instructions
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
75 .arch armv8-a
76 .fpu crypto-neon-fp-armv8
118 vld1.64 {q11-q12}, [buf]!
155 // Assumes len >= 16.
167 vld1.64 {q0-q1}, [buf]!
168 vld1.64 {q2-q3}, [buf]!
169 vld1.64 {q4-q5}, [buf]!
[all …]

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