emulex/benet/be_hw.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (C) 2005-2016 Broadcom.
7  * linux-drivers@emulex.com
17  * it writes the register with hi=1 and the upper bits of the physical address
20  * bits in the address. It must poll the ready bit until the command is
33 #define SLIPORT_SEMAPHORE_OFFSET_SH		0x94  /* PCI-CFG offset */
44 #define POST_STAGE_HOST_RDY 		0x2 /* Host has given go-ahed to FW */
90 #define PCICFG_PM_CONTROL_MASK			0x108	/* bits 3 & 8 */
109 #define SLI_INTF_HINT1_SHIFT			16
127 #define DB_EQ_RING_ID_MASK		0x1FF	/* bits 0 - 8 */
128 #define DB_EQ_RING_ID_EXT_MASK		0x3e00  /* bits 9-13 */
129 #define DB_EQ_RING_ID_EXT_MASK_SHIFT	(2) /* qid bits 9-13 placing at 11-15 */
136 #define DB_EQ_NUM_POPPED_SHIFT		(16)	/* bits 16 - 28 */
140 #define DB_EQ_R2I_DLY_SHIFT		(30)    /* bits 30 - 31 */
154 #define DB_CQ_RING_ID_MASK		0x3FF	/* bits 0 - 9 */
155 #define DB_CQ_RING_ID_EXT_MASK		0x7C00	/* bits 10-14 */
156 #define DB_CQ_RING_ID_EXT_MASK_SHIFT	(1)	/* qid bits 10-14
157 						 placing at 11-15 */
160 #define DB_CQ_NUM_POPPED_SHIFT		(16) 	/* bits 16 - 28 */
166 #define DB_TXULP_RING_ID_MASK		0x7FF	/* bits 0 - 10 */
168 #define DB_TXULP_NUM_POSTED_SHIFT	(16)	/* bits 16 - 29 */
169 #define DB_TXULP_NUM_POSTED_MASK	0x3FFF	/* bits 16 - 29 */
173 #define DB_RQ_RING_ID_MASK		0x3FF	/* bits 0 - 9 */
175 #define DB_RQ_NUM_POSTED_SHIFT		(24)	/* bits 24 - 31 */
179 #define DB_MCCQ_RING_ID_MASK		0x7FF	/* bits 0 - 10 */
181 #define DB_MCCQ_NUM_POSTED_SHIFT	(16)	/* bits 16 - 29 */
202 #define EQ_ENTRY_RES_ID_MASK 		0xFFFF	/* bits 16 - 31 */
203 #define EQ_ENTRY_RES_ID_SHIFT 		16
215 	__le32 frag_len;		/* dword 3: bits 0 - 15 */
238 	u8 len[16];		/* dword 3 */
239 	u8 vlan_tag[16];
244 #define TX_HDR_WRB_NUM_SHIFT		13		/* word 2: bits 13:17 */
245 #define TX_HDR_WRB_NUM_MASK		0x1F		/* word 2: bits 13:17 */
270 	u8 wrb_index[16];	/* dword 0 */
275 	u8 user_bytes[16];	/* dword 1 */
281 	u8 pkts[16];		/* dword 3 */
303 	u8 vlan_tag[16];	/* dword 0 */
337 	u8 vlan_tag[16];	/* dword 0 */