amd/atl/reg_fields.h

1 /* SPDX-License-Identifier: GPL-2.0 */
28  *	Rev	Fieldname	Bits
46  *	Rev	Fieldname	Bits
69  *	Rev	Fieldname	Bits
77  *	DF4	DstFabricID	[27:16]
80  *	DF4p5	DstFabricID	[23:16]
85 #define DF4_DST_FABRIC_ID	GENMASK(27, 16)
86 #define DF4p5_DST_FABRIC_ID	GENMASK(23, 16)
94  *	Rev	Fieldname	Bits
100  *	DF3	DieIdMask	[18:16]
110 #define DF3_DIE_ID_MASK		GENMASK(18, 16)
119  *	Rev	Fieldname	Bits
137  *	Rev	Fieldname	Bits
158  *	Rev	Fieldname	Bits
180  *	Rev	Fieldname	Bits
199  *	Rev	Fieldname	Bits
221  *	Rev	Fieldname	Bits
261  *	Rev	Fieldname	Bits
276 /* Follow reference code by including reserved bits for simplicity. */
285  *	Rev	Fieldname	Bits
304  *	Rev	Fieldname	Bits
327  *	Rev	Fieldname	Bits
352  *	Rev	Fieldname	Bits
378  *	Rev	Fieldname	Bits
402  *	Rev	Fieldname	Bits
423  *	Rev	Fieldname		Bits
427  *	D18F2x90 [Non-power-of-2 channel Configuration Register for COH_ST DRAM Address Maps]
442  *	Rev	Fieldname	Bits
460  *	Rev	Fieldname	Bits
467  *	DF4	MinorRevision	[23:16]
468  *	DF4p5	MinorRevision	[23:16]
470 #define DF_MINOR_REVISION	GENMASK(23, 16)
478  *	Rev	Fieldname	Bits
483  *	DF3	NodeIdMask	[25:16]
486  *	DF3p5	NodeIdMask	[31:16]
489  *	DF4	NodeIdMask	[31:16]
490  *	DF4p5	NodeIdMask	[31:16]
492 #define DF3_NODE_ID_MASK	GENMASK(25, 16)
493 #define DF4_NODE_ID_MASK	GENMASK(31, 16)
501  *	Rev	Fieldname	Bits
523  *	Rev	Fieldname	Bits
543  *	Rev	Fieldname	Bits
564  *	Rev	Fieldname	Bits
567  *	DF2	SocketIdMask	[23:16]
573  *	DF3p5	SocketIdMask	[31:16]
576  *	DF4	SocketIdMask	[31:16]
577  *	DF4p5	SocketIdMask	[31:16]
579 #define DF2_SOCKET_ID_MASK	GENMASK(23, 16)
581 #define DF4_SOCKET_ID_MASK	GENMASK(31, 16)
589  *		Rev	Fieldname	Bits