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/linux-6.12.1/drivers/staging/media/atomisp/pci/
Dcss_receiver_2400_common_defs.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit …
29 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit …
30 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit lega…
31 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit …
32 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit …
33 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 …
34 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 …
35 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 …
36 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 …
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Dcss_receiver_2400_defs.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define CSS_RECEIVER_IMG_PROC_RF_ADDR 10
34 #define CSS_RECEIVER_PRED10_VAL 10
50 …VER_2400_GEN_SHORT_STR_DATA_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB - 1)
51 …VER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB - 1)
52 …VER_2400_GEN_SHORT_STR_CH_ID_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH - 1)
70 #define _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX 10
90 /* Interrupt bits for IRQ_STATUS and IRQ_ENABLE registers */
101 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT 10
123 #define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_CAUSE_ "Data time-out"
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/linux-6.12.1/drivers/staging/media/atomisp/pci/css_2401_system/hrt/
Dmipi_backend_common_defs.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit …
29 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit …
30 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit lega…
31 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit …
32 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit …
33 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 …
34 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 …
35 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 …
36 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 …
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/linux-6.12.1/drivers/iio/adc/
Dmax1363.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2008-2010 Jonathan Cameron
7 * Copyright (C) 2002-2004 Stefan Eletzhofer
52 /* think about including max11600 etc - more settings */
59 /* max1363 only - though don't care on others.
80 /* max123{6-9} only */
83 /* max1363 only - merely part of channel selects or don't care for others */
88 /* max1363 strictly 0x06 - but doesn't matter */
95 * struct max1363_mode - scan mode information
123 * struct max1363_chip_info - chip specifc information
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/linux-6.12.1/Documentation/userspace-api/media/v4l/
Dpixfmt-yuv-planar.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. planar-yuv:
12 - Semi-planar formats use two planes. The first plane is the luma plane and
16 - Fully planar formats use three planes to store the Y, Cb and Cr components
26 and applications that support the multi-planar API, described in
27 :ref:`planar-apis`. Unless explicitly documented as supporting non-contiguous
31 Semi-Planar YUV Formats
46 For non-contiguous formats, no constraints are enforced by the format on the
49 All components are stored with the same number of bits per component.
57 .. flat-table:: Overview of Semi-Planar YUV Formats
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Dpixfmt-srggb10p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB10P:
4 .. _v4l2-pix-fmt-sbggr10p:
5 .. _v4l2-pix-fmt-sgbrg10p:
6 .. _v4l2-pix-fmt-sgrbg10p:
16 10-bit packed Bayer formats
22 These four pixel formats are packed raw sRGB / Bayer formats with 10
23 bits per sample. Every four consecutive samples are packed into 5
24 bytes. Each of the first 4 bytes contain the 8 high order bits
26 bits of each pixel, in the same order.
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/linux-6.12.1/arch/arm/mach-omap2/
Dprcm-common.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
9 * Copyright (C) 2007-2009 Nokia Corporation
30 /* Chip-specific module offsets */
37 #define OMAP3430_IVA2_MOD -0x800
66 /* 24XX register bits shared between CM & PRM registers */
68 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
91 #define OMAP24XX_EN_GPT8_SHIFT 10
92 #define OMAP24XX_EN_GPT8_MASK (1 << 10)
108 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
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/linux-6.12.1/arch/arc/include/asm/
Ddisasm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
32 #define BITS(word, s, e) (((word) >> (s)) & (~((-2) << ((e) - (s))))) macro
34 #define MAJOR_OPCODE(word) (BITS((word), 27, 31))
35 #define MINOR_OPCODE(word) (BITS((word), 16, 21))
36 #define FIELD_A(word) (BITS((word), 0, 5))
37 #define FIELD_B(word) ((BITS((word), 12, 14)<<3) | \
38 (BITS((word), 24, 26)))
39 #define FIELD_C(word) (BITS((word), 6, 11))
41 #define FIELD_s12(word) sign_extend(((BITS((word), 0, 5) << 6) | \
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/linux-6.12.1/include/uapi/linux/usb/
Dch11.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
16 * From USB 2.0 spec Table 11-13, offset 7, a hub can
17 * have up to 255 ports. The most yet reported is 10.
24 /* See USB 3.1 spec Table 10-5 */
36 * See USB 3.1 spec Table 10-12
44 * See USB 2.0 spec Table 11-16
48 #define HUB_GET_TT_STATE 10
53 * See USB 3.0 spec Table 10-6
60 * See USB 2.0 spec Table 11-17
67 * See USB 2.0 spec Table 11-17
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/linux-6.12.1/drivers/crypto/hisilicon/sec2/
Dsec_crypto.h1 /* SPDX-License-Identifier: GPL-2.0 */
97 * mac_len: 0~4 bits
98 * a_key_len: 5~10 bits
99 * a_alg: 11~16 bits
104 * c_icv_len: 0~5 bits
105 * c_width: 6~8 bits
106 * c_key_len: 9~11 bits
107 * c_mode: 12~15 bits
111 /* c_alg: 0~3 bits */
116 * a_len: 0~23 bits
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/linux-6.12.1/drivers/media/radio/si470x/
Dradio-si470x.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * drivers/media/radio/si470x/radio-si470x.h
12 #define DRIVER_NAME "radio-si470x"
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ioctl.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-event.h>
28 #include <media/v4l2-device.h>
41 #define DEVICEID_PN 0xf000 /* bits 15..12: Part Number */
42 #define DEVICEID_MFGID 0x0fff /* bits 11..00: Manufacturer ID */
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/linux-6.12.1/drivers/cpufreq/
Dpowernow-k7.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * - We cli/sti on stepping A0 CPUs around the FID/VID transition.
13 * - We disable half multipliers if ACPI is used on A0 stepping CPUs.
38 #include "powernow-k7.h"
41 u8 signature[10];
64 } bits; member
77 /* divide by 10 to get FID. */
82 150, 225, 160, 165, 170, 180, -1, -1,
95 static unsigned int minimum_speed = -1;
107 delta = (fsbspeed > f) ? fsbspeed - f : f - fsbspeed; in check_fsb()
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/linux-6.12.1/drivers/gpu/drm/exynos/
Dregs-mixer.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Cloned from drivers/media/video/s5p-tv/regs-mixer.h
6 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
65 /* generates mask for range of bits */
67 (((2 << ((high_bit) - (low_bit))) - 1) << (low_bit))
72 /* bits for MXR_STATUS */
82 /* bits for MXR_CFG */
87 #define MXR_CFG_RGB601 (0 << 10)
88 #define MXR_CFG_RGB709 (1 << 10)
110 /* bits for MXR_VIDEO_CFG */
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/linux-6.12.1/arch/x86/math-emu/
DREADME1 +---------------------------------------------------------------------------+
2 | wm-FPU-emu an FPU emulator for 80386 and 80486SX microprocessors. |
6 | Australia. E-mail billm@melbpc.org.au |
21 +---------------------------------------------------------------------------+
25 wm-FPU-emu is an FPU emulator for Linux. It is derived from wm-emu387
27 msdos); wm-emu387 was in turn based upon emu387 which was written by
31 My target FPU for wm-FPU-emu is that described in the Intel486
40 wm-FPU-emu does not implement all of the behaviour of the 80486 FPU,
52 --Bill Metzenthen
56 ----------------------- Internals of wm-FPU-emu -----------------------
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/linux-6.12.1/include/uapi/drm/
Ddrm_fourcc.h39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
143 /* 10 bpp Red (direct relationship between channel value and brightness) */
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/linux-6.12.1/drivers/net/ethernet/dec/tulip/
Dpnic2.c5 Written/copyright 1994-2001 by Donald Becker.
15 /* Understanding the PNIC_II - everything is this file is based
18 * As I understand things, here are the registers and bits that
23 * CSR 6 (mask = 0xfe3bd1fd of bits not to change)
24 * -----
25 * Bit 24 - SCR
26 * Bit 23 - PCS
27 * Bit 22 - TTM (Trasmit Threshold Mode)
28 * Bit 18 - Port Select
29 * Bit 13 - Start - 1, Stop - 0 Transmissions
[all …]
/linux-6.12.1/drivers/net/ipa/reg/
Dipa_reg-v5.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
6 #include <linux/bits.h>
32 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
39 /* Bits 17-18 reserved */
44 /* Bits 28-29 reserved */
62 [HPS_DPS_CMDQS] = BIT(10),
95 /* Bits 29-31 reserved */
110 /* Bits 8-31 reserved */
118 /* Bits 8-15 reserved */
[all …]
/linux-6.12.1/drivers/gpu/drm/mediatek/
Dmtk_disp_gamma.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/soc/mediatek/mtk-cmdq.h>
35 /* For 10 bit LUT layout, R/G/B are in the same register */
37 #define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10)
54 * struct mtk_disp_gamma - Display Gamma driver structure
71 return clk_prepare_enable(gamma->clk); in mtk_gamma_clk_enable()
78 clk_disable_unprepare(gamma->clk); in mtk_gamma_clk_disable()
85 if (gamma && gamma->data) in mtk_gamma_get_lut_size()
86 return gamma->data->lut_size; in mtk_gamma_get_lut_size()
93 int last_entry = lut_size - 1; in mtk_gamma_lut_is_descending()
[all …]
/linux-6.12.1/drivers/ras/amd/atl/
Dreg_fields.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 * Rev Fieldname Bits
46 * Rev Fieldname Bits
69 * Rev Fieldname Bits
94 * Rev Fieldname Bits
119 * Rev Fieldname Bits
137 * Rev Fieldname Bits
158 * Rev Fieldname Bits
180 * Rev Fieldname Bits
199 * Rev Fieldname Bits
[all …]
/linux-6.12.1/drivers/staging/media/atomisp/pci/runtime/isys/src/
Drx.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2010 - 2015, Intel Corporation.
25 hrt_data bits = receiver_port_reg_load(RX0_ID, in ia_css_isys_rx_enable_all_interrupts() local
29 bits |= (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT) | in ia_css_isys_rx_enable_all_interrupts()
49 _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, bits); in ia_css_isys_rx_enable_all_interrupts()
103 unsigned int bits; in ia_css_isys_rx_get_irq_info() local
106 bits = ia_css_isys_rx_get_interrupt_reg(port); in ia_css_isys_rx_get_irq_info()
107 *irq_infos = ia_css_isys_rx_translate_irq_infos(bits); in ia_css_isys_rx_get_irq_info()
110 /* Translate register bits to CSS API enum mask */
111 unsigned int ia_css_isys_rx_translate_irq_infos(unsigned int bits) in ia_css_isys_rx_translate_irq_infos() argument
[all …]
/linux-6.12.1/drivers/hwmon/pmbus/
Dmp2888.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
27 #define MP2888_TEMP_UNIT 10
28 #define MP2888_MAX_PHASE 10
46 return -ENODATA; in mp2888_read_byte_data()
57 * , bits 0-2. The value is selected as below: in mp2888_current_sense_gain_and_resolution_get()
58 * 00b - 5µA/A, 01b - 8.5µA/A, 10b - 9.7µA/A, 11b - 10µA/A. Other in mp2888_current_sense_gain_and_resolution_get()
67 data->curr_sense_gain = 85; in mp2888_current_sense_gain_and_resolution_get()
70 data->curr_sense_gain = 97; in mp2888_current_sense_gain_and_resolution_get()
73 data->curr_sense_gain = 100; in mp2888_current_sense_gain_and_resolution_get()
[all …]
/linux-6.12.1/drivers/net/ethernet/emulex/benet/
Dbe_hw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
17 * it writes the register with hi=1 and the upper bits of the physical address
20 * bits in the address. It must poll the ready bit until the command is
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
90 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
127 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
128 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
[all …]
/linux-6.12.1/include/rdma/
Dopa_port_info.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright (c) 2014-2020 Intel Corporation. All rights reserved.
17 #define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */
21 #define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */
22 #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */
23 #define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */
24 #define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */
37 #define OPA_LINKDOWN_REASON_BAD_MID_TAIL 10
61 /* 34 -reserved */
64 /* 37-38 reserved */
[all …]
/linux-6.12.1/drivers/crypto/qce/
Dregs-v5.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
105 /* Register bits - REG_VERSION */
113 /* Register bits - REG_STATUS */
126 #define CRYPTO_STATE_SHIFT 10
127 #define CRYPTO_STATE_MASK GENMASK(13, 10)
139 /* Register bits - REG_STATUS2 */
143 /* Register bits - REG_CONFIG */
156 #define REQ_SIZE_ENUM_11_BEAT 10
169 #define IRQ_ENABLES_SHIFT 10
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/linux-6.12.1/arch/m68k/fpsp040/
Dbindec.S12 | value in memory; d0 contains the k-factor sign-extended
13 | to 32-bits. The input may be either normalized,
18 | Saves and Modifies: D2-D7,A2,FP2
23 | The k-factor is saved for use in d7. Clear the
31 | ILOG is the log base 10 of the input value. It is
45 | k-factor can dictate either the total number of digits,
53 | SCALE is equal to 10^ISCALE, where ISCALE is the number
57 | 10^^(abs(ISCALE)) using a rounding mode which is a
64 | only one rounding error. The grs bits are collected in
67 | A9. Scale X -> Y.
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