1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/soc/mediatek/mtk-cmdq.h>
35 /* For 10 bit LUT layout, R/G/B are in the same register */
37 #define DISP_GAMMA_LUT_10BIT_G			GENMASK(19, 10)
54  * struct mtk_disp_gamma - Display Gamma driver structure
71 	return clk_prepare_enable(gamma->clk);  in mtk_gamma_clk_enable()
78 	clk_disable_unprepare(gamma->clk);  in mtk_gamma_clk_disable()
85 	if (gamma && gamma->data)  in mtk_gamma_get_lut_size()
86 		return gamma->data->lut_size;  in mtk_gamma_get_lut_size()
93 	int last_entry = lut_size - 1;  in mtk_gamma_lut_is_descending()
102  * SoCs supporting 12-bits LUTs are using a new register layout that does
103  * always support (by HW) both 12-bits and 10-bits LUT but, on those, we
104  * ignore the support for 10-bits in this driver and always use 12-bits.
107  * - SoC HW support 9/10-bits LUT only
108  *   - Old register layout
109  *     - 10-bits LUT supported
110  *     - 9-bits LUT not supported
111  * - SoC HW support both 10/12bits LUT
112  *   - New register layout
113  *     - 12-bits LUT supported
114  *     - 10-its LUT not supported
119 	void __iomem *lut0_base = gamma->regs + DISP_GAMMA_LUT;  in mtk_gamma_set()
120 	void __iomem *lut1_base = gamma->regs + DISP_GAMMA_LUT1;  in mtk_gamma_set()
122 	u8 lut_bits = gamma->data->lut_bits;  in mtk_gamma_set()
128 	if (!state->gamma_lut)  in mtk_gamma_set()
131 	num_lut_banks = gamma->data->lut_size / gamma->data->lut_bank_size;  in mtk_gamma_set()
132 	lut = (struct drm_color_lut *)state->gamma_lut->data;  in mtk_gamma_set()
134 	/* Switch to 12 bits data mode if supported */  in mtk_gamma_set()
143 			writel(lbank_val, gamma->regs + DISP_GAMMA_BANK);  in mtk_gamma_set()
146 		for (i = 0; i < gamma->data->lut_bank_size; i++) {  in mtk_gamma_set()
147 			int n = cur_bank * gamma->data->lut_bank_size + i;  in mtk_gamma_set()
154 			if (!gamma->data->lut_diff || (i % 2 == 0)) {  in mtk_gamma_set()
165 				diff.red = lut[n].red - lut[n - 1].red;  in mtk_gamma_set()
168 				diff.green = lut[n].green - lut[n - 1].green;  in mtk_gamma_set()
171 				diff.blue = lut[n].blue - lut[n - 1].blue;  in mtk_gamma_set()
190 	cfg_val = readl(gamma->regs + DISP_GAMMA_CFG);  in mtk_gamma_set()
192 	if (!gamma->data->has_dither) {  in mtk_gamma_set()
194 		if (mtk_gamma_lut_is_descending(lut, gamma->data->lut_size - 1))  in mtk_gamma_set()
206 	writel(cfg_val, gamma->regs + DISP_GAMMA_CFG);  in mtk_gamma_set()
219 	mtk_ddp_write(cmdq_pkt, sz, &gamma->cmdq_reg, gamma->regs, DISP_GAMMA_SIZE);  in mtk_gamma_config()
220 	if (gamma->data && gamma->data->has_dither)  in mtk_gamma_config()
221 		mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc,  in mtk_gamma_config()
229 	writel(GAMMA_EN, gamma->regs + DISP_GAMMA_EN);  in mtk_gamma_start()
236 	writel_relaxed(0x0, gamma->regs + DISP_GAMMA_EN);  in mtk_gamma_stop()
257 	struct device *dev = &pdev->dev;  in mtk_disp_gamma_probe()
264 		return -ENOMEM;  in mtk_disp_gamma_probe()
266 	priv->clk = devm_clk_get(dev, NULL);  in mtk_disp_gamma_probe()
267 	if (IS_ERR(priv->clk))  in mtk_disp_gamma_probe()
268 		return dev_err_probe(dev, PTR_ERR(priv->clk),  in mtk_disp_gamma_probe()
272 	priv->regs = devm_ioremap_resource(dev, res);  in mtk_disp_gamma_probe()
273 	if (IS_ERR(priv->regs))  in mtk_disp_gamma_probe()
274 		return dev_err_probe(dev, PTR_ERR(priv->regs),  in mtk_disp_gamma_probe()
278 	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);  in mtk_disp_gamma_probe()
280 		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");  in mtk_disp_gamma_probe()
283 	priv->data = of_device_get_match_data(dev);  in mtk_disp_gamma_probe()
295 	component_del(&pdev->dev, &mtk_disp_gamma_component_ops);  in mtk_disp_gamma_remove()
301 	.lut_bits = 10,
307 	.lut_bits = 10,
320 	{ .compatible = "mediatek,mt8173-disp-gamma",
322 	{ .compatible = "mediatek,mt8183-disp-gamma",
324 	{ .compatible = "mediatek,mt8195-disp-gamma",
334 		.name	= "mediatek-disp-gamma",