Lines Matching +full:10 +full:- +full:bits
1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
9 * Copyright (C) 2007-2009 Nokia Corporation
30 /* Chip-specific module offsets */
37 #define OMAP3430_IVA2_MOD -0x800
66 /* 24XX register bits shared between CM & PRM registers */
68 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
91 #define OMAP24XX_EN_GPT8_SHIFT 10
92 #define OMAP24XX_EN_GPT8_MASK (1 << 10)
108 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
109 #define OMAP2430_EN_GPIO5_SHIFT 10
110 #define OMAP2430_EN_GPIO5_MASK (1 << 10)
122 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
130 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
153 #define OMAP24XX_ST_GPT8_SHIFT 10
154 #define OMAP24XX_ST_GPT8_MASK (1 << 10)
170 /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
173 #define OMAP2430_ST_GPIO5_SHIFT 10
174 #define OMAP2430_ST_GPIO5_MASK (1 << 10)
188 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
194 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
202 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
207 /* 3430 register bits shared between CM & PRM registers */
209 /* CM_REVISION, PRM_REVISION shared bits */
213 /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
216 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
247 #define OMAP3430_EN_MCBSP5_MASK (1 << 10)
248 #define OMAP3430_EN_MCBSP5_SHIFT 10
256 /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
260 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
289 #define OMAP3430_ST_MCBSP5_SHIFT 10
290 #define OMAP3430_ST_MCBSP5_MASK (1 << 10)
304 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
312 /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
318 /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
322 /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
339 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
344 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
360 #define OMAP3430_EN_GPT9_MASK (1 << 10)
361 #define OMAP3430_EN_GPT9_SHIFT 10
377 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
378 /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
379 * be ST_* bits instead? */
387 /* CM_IDLEST_PER, PM_WKST_PER shared bits */
402 #define OMAP3430_ST_GPT9_SHIFT 10
403 #define OMAP3430_ST_GPT9_MASK (1 << 10)
419 /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
437 * omap_test_timeout - busy-loop, testing a condition
457 * struct omap_prcm_irq - describes a PRCM interrupt bit
462 * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
464 * the registers are concatenated, so @offset could be > 31 on these systems -
475 * struct omap_prcm_irq_setup - PRCM interrupt controller details
481 * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
491 * @suspended: set to true after Linux suspend code has called our ->prepare()
532 * struct omap_prcm_init_data - PRCM driver init data