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/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dbrcm,bcm63xx-spi.yaml64 reg = <0x10000800 0x70c>;
70 #size-cells = <0>;
/linux-6.12.1/arch/mips/pci/
Dpci-mt7620.c24 #define RALINK_PCI_IO_MAP_BASE 0x10160000
25 #define RALINK_PCI_MEMORY_BASE 0x0
29 #define RALINK_CLKCFG1 0x30
30 #define RALINK_GPIOMODE 0x60
32 #define PPLL_CFG1 0x9c
35 #define PPLL_DRV 0xa0
43 #define RALINK_PCI_PCICFG_ADDR 0x00
46 #define RALINK_PCI_PCIENA 0x0C
49 #define RALINK_PCI_CONFIG_ADDR 0x20
50 #define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
[all …]
/linux-6.12.1/drivers/media/common/b2c2/
Dflexcop-reg.h11 FLEXCOP_UNK = 0,
18 FC_UNK = 0,
32 FC_USB = 0,
47 #define fc_data_Tag_ID_DVB 0x3e
48 #define fc_data_Tag_ID_ATSC 0x3f
49 #define fc_data_Tag_ID_IDSB 0x8b
51 #define fc_key_code_default 0x1
52 #define fc_key_code_even 0x2
53 #define fc_key_code_odd 0x3
64 FC_WRITE = 0,
[all …]
/linux-6.12.1/arch/mips/boot/dts/brcm/
Dbcm6358.dtsi13 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
33 #clock-cells = <0>;
47 #address-cells = <0>;
63 reg = <0xfffe0004 0x4>;
69 reg = <0xfffe0008 0x4>;
74 offset = <0x0>;
75 mask = <0x1>;
81 reg = <0xfffe000c 0x8>,
[all …]
Dbcm6362.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
42 #clock-cells = <0>;
58 #address-cells = <0>;
74 reg = <0x10000004 0x4>;
80 reg = <0x10000008 0x4>;
85 offset = <0x0>;
86 mask = <0x1>;
[all …]
Dbcm6368.dtsi13 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
33 #clock-cells = <0>;
48 #address-cells = <0>;
64 reg = <0x10000004 0x4>;
70 reg = <0x10000008 0x4>;
75 offset = <0x0>;
76 mask = <0x1>;
82 reg = <0x10000010 0x4>;
[all …]
Dbcm63268.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
42 #clock-cells = <0>;
58 #address-cells = <0>;
74 reg = <0x10000004 0x4>;
80 reg = <0x10000008 0x4>;
85 offset = <0x0>;
86 mask = <0x1>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/hisilicon/
Dhikey970-pinctrl.dtsi16 reg = <0x0 0xe896c000 0x0 0x72c>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
22 pinctrl-single,gpio-range = <&range 0 82 0>;
26 0x054 MUX_M2 /* UART0_RXD */
27 0x058 MUX_M2 /* UART0_TXD */
33 0x700 MUX_M2 /* UART2_CTS_N */
34 0x704 MUX_M2 /* UART2_RTS_N */
35 0x708 MUX_M2 /* UART2_RXD */
[all …]
/linux-6.12.1/drivers/accel/habanalabs/goya/
Dgoya_coresight.c18 #define SPMU_EVENT_TYPES_OFFSET 0x400
220 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", in goya_coresight_timeout()
225 return 0; in goya_coresight_timeout()
243 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in goya_config_stm()
251 WREG32(base_reg + 0xE80, 0x80004); in goya_config_stm()
252 WREG32(base_reg + 0xD64, 7); in goya_config_stm()
253 WREG32(base_reg + 0xD60, 0); in goya_config_stm()
254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in goya_config_stm()
255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask)); in goya_config_stm()
256 WREG32(base_reg + 0xD60, 1); in goya_config_stm()
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/linux-6.12.1/drivers/phy/samsung/
Dphy-exynos4x12-usb2.c18 #define EXYNOS_4x12_UPHYPWR 0x0
20 #define EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND BIT(0)
55 #define EXYNOS_4x12_UPHYCLK 0x4
57 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK (0x7 << 0)
58 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET 0
59 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6 (0x0 << 0)
60 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ (0x1 << 0)
61 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
62 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2 (0x3 << 0)
63 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ (0x4 << 0)
[all …]
Dphy-exynos5250-usb2.c16 #define EXYNOS_5250_REFCLKSEL_CRYSTAL 0x0
17 #define EXYNOS_5250_REFCLKSEL_XO 0x1
18 #define EXYNOS_5250_REFCLKSEL_CLKCORE 0x2
20 #define EXYNOS_5250_FSEL_9MHZ6 0x0
21 #define EXYNOS_5250_FSEL_10MHZ 0x1
22 #define EXYNOS_5250_FSEL_12MHZ 0x2
23 #define EXYNOS_5250_FSEL_19MHZ2 0x3
24 #define EXYNOS_5250_FSEL_20MHZ 0x4
25 #define EXYNOS_5250_FSEL_24MHZ 0x5
26 #define EXYNOS_5250_FSEL_50MHZ 0x7
[all …]
/linux-6.12.1/drivers/gpu/drm/radeon/
Drv6xxd.h27 #define SPLL_CNTL_MODE 0x60c
30 #define GENERAL_PWRMGT 0x618
31 # define GLOBAL_PWRMGT_EN (1 << 0)
47 #define MCLK_PWRMGT_CNTL 0x624
48 # define MPLL_PWRMGT_OFF (1 << 0)
78 #define MPLL_FREQ_LEVEL_0 0x6e8
79 # define LEVEL0_MPLL_POST_DIV(x) ((x) << 0)
80 # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0)
82 # define LEVEL0_MPLL_FB_DIV_MASK (0xfff << 8)
84 # define LEVEL0_MPLL_REF_DIV_MASK (0x3f << 20)
[all …]
Dsumod.h30 #define RCU_FW_VERSION 0x30c
32 #define RCU_PWR_GATING_SEQ0 0x408
33 #define RCU_PWR_GATING_SEQ1 0x40c
34 #define RCU_PWR_GATING_CNTL 0x410
35 # define PWR_GATING_EN (1 << 0)
36 # define RSVD_MASK (0x3 << 1)
38 # define PCV_MASK (0x1f << 3)
41 # define PCP_MASK (0xf << 8)
44 # define RPW_MASK (0xf << 16)
47 # define ID_MASK (0xf << 24)
[all …]
/linux-6.12.1/drivers/usb/dwc3/
Ddwc3-am62.c23 #define USBSS_PID 0x0
24 #define USBSS_OVERCURRENT_CTRL 0x4
25 #define USBSS_PHY_CONFIG 0x8
26 #define USBSS_PHY_TEST 0xc
27 #define USBSS_CORE_STAT 0x14
28 #define USBSS_HOST_VBUS_CTRL 0x18
29 #define USBSS_MODE_CONTROL 0x1c
30 #define USBSS_WAKEUP_CONFIG 0x30
31 #define USBSS_WAKEUP_STAT 0x34
32 #define USBSS_OVERRIDE_CONFIG 0x38
[all …]
/linux-6.12.1/drivers/gpu/drm/tegra/
Ddc.h176 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000
177 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
179 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
180 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
181 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008
182 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
183 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
184 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010
185 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
186 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
[all …]
/linux-6.12.1/drivers/net/wireless/ath/ath9k/
Dpci.c25 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
26 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
27 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
32 0x0029,
34 0x2096),
38 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
42 0x002A,
44 0x1C71),
47 0x002A,
49 0xE01F),
[all …]
/linux-6.12.1/drivers/accel/habanalabs/gaudi/
Dgaudi_coresight.c17 #define SPMU_EVENT_TYPES_OFFSET 0x400
382 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", in gaudi_coresight_timeout()
387 return 0; in gaudi_coresight_timeout()
405 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in gaudi_config_stm()
413 WREG32(base_reg + 0xE80, 0x80004); in gaudi_config_stm()
414 WREG32(base_reg + 0xD64, 7); in gaudi_config_stm()
415 WREG32(base_reg + 0xD60, 0); in gaudi_config_stm()
416 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in gaudi_config_stm()
417 WREG32(base_reg + 0xD60, 1); in gaudi_config_stm()
418 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); in gaudi_config_stm()
[all …]
/linux-6.12.1/include/linux/mfd/mt6331/
Dregisters.h10 #define MT6331_STRUP_CON0 0x0
11 #define MT6331_STRUP_CON2 0x2
12 #define MT6331_STRUP_CON3 0x4
13 #define MT6331_STRUP_CON4 0x6
14 #define MT6331_STRUP_CON5 0x8
15 #define MT6331_STRUP_CON6 0xA
16 #define MT6331_STRUP_CON7 0xC
17 #define MT6331_STRUP_CON8 0xE
18 #define MT6331_STRUP_CON9 0x10
19 #define MT6331_STRUP_CON10 0x12
[all …]
/linux-6.12.1/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_reg.h12 #define ANALOGIX_DP_TX_SW_RESET 0x14
13 #define ANALOGIX_DP_FUNC_EN_1 0x18
14 #define ANALOGIX_DP_FUNC_EN_2 0x1C
15 #define ANALOGIX_DP_VIDEO_CTL_1 0x20
16 #define ANALOGIX_DP_VIDEO_CTL_2 0x24
17 #define ANALOGIX_DP_VIDEO_CTL_3 0x28
19 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C
20 #define ANALOGIX_DP_VIDEO_CTL_10 0x44
22 #define ANALOGIX_DP_SPDIF_AUDIO_CTL_0 0xD8
24 #define ANALOGIX_DP_PLL_REG_1 0xfc
[all …]
/linux-6.12.1/drivers/pci/controller/
Dpcie-mt7621.c36 #define PCIE_FTS_NUM 0x70c
38 #define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
41 #define RALINK_PCI_PCICFG_ADDR 0x0000
42 #define RALINK_PCI_PCIMSK_ADDR 0x000c
43 #define RALINK_PCI_CONFIG_ADDR 0x0020
44 #define RALINK_PCI_CONFIG_DATA 0x0024
45 #define RALINK_PCI_MEMBASE 0x0028
46 #define RALINK_PCI_IOBASE 0x002c
49 #define RALINK_PCI_ID 0x0030
50 #define RALINK_PCI_CLASS 0x0034
[all …]
/linux-6.12.1/drivers/clk/stm32/
Dstm32mp25_rcc.h10 #define RCC_SECCFGR0 0x0
11 #define RCC_SECCFGR1 0x4
12 #define RCC_SECCFGR2 0x8
13 #define RCC_SECCFGR3 0xC
14 #define RCC_PRIVCFGR0 0x10
15 #define RCC_PRIVCFGR1 0x14
16 #define RCC_PRIVCFGR2 0x18
17 #define RCC_PRIVCFGR3 0x1C
18 #define RCC_RCFGLOCKR0 0x20
19 #define RCC_RCFGLOCKR1 0x24
[all …]
/linux-6.12.1/drivers/net/ethernet/cavium/liquidio/
Dcn66xx_regs.h26 #define CN6XXX_XPANSION_BAR 0x30
28 #define CN6XXX_MSI_CAP 0x50
29 #define CN6XXX_MSI_ADDR_LO 0x54
30 #define CN6XXX_MSI_ADDR_HI 0x58
31 #define CN6XXX_MSI_DATA 0x5C
33 #define CN6XXX_PCIE_CAP 0x70
34 #define CN6XXX_PCIE_DEVCAP 0x74
35 #define CN6XXX_PCIE_DEVCTL 0x78
36 #define CN6XXX_PCIE_LINKCAP 0x7C
37 #define CN6XXX_PCIE_LINKCTL 0x80
[all …]
/linux-6.12.1/include/sound/
Dhda_verbs.h12 #define AC_NODE_ROOT 0x00
18 AC_GRP_AUDIO_FUNCTION = 0x01,
19 AC_GRP_MODEM_FUNCTION = 0x02,
34 AC_WID_VENDOR = 0x0f /* Vendor specific */
40 #define AC_VERB_GET_STREAM_FORMAT 0x0a00
41 #define AC_VERB_GET_AMP_GAIN_MUTE 0x0b00
42 #define AC_VERB_GET_PROC_COEF 0x0c00
43 #define AC_VERB_GET_COEF_INDEX 0x0d00
44 #define AC_VERB_PARAMETERS 0x0f00
45 #define AC_VERB_GET_CONNECT_SEL 0x0f01
[all …]

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