Lines Matching +full:0 +full:x70c

26 #define     CN6XXX_XPANSION_BAR             0x30
28 #define CN6XXX_MSI_CAP 0x50
29 #define CN6XXX_MSI_ADDR_LO 0x54
30 #define CN6XXX_MSI_ADDR_HI 0x58
31 #define CN6XXX_MSI_DATA 0x5C
33 #define CN6XXX_PCIE_CAP 0x70
34 #define CN6XXX_PCIE_DEVCAP 0x74
35 #define CN6XXX_PCIE_DEVCTL 0x78
36 #define CN6XXX_PCIE_LINKCAP 0x7C
37 #define CN6XXX_PCIE_LINKCTL 0x80
38 #define CN6XXX_PCIE_SLOTCAP 0x84
39 #define CN6XXX_PCIE_SLOTCTL 0x88
41 #define CN6XXX_PCIE_ENH_CAP 0x100
42 #define CN6XXX_PCIE_UNCORR_ERR_STATUS 0x104
43 #define CN6XXX_PCIE_UNCORR_ERR_MASK 0x108
44 #define CN6XXX_PCIE_UNCORR_ERR 0x10C
45 #define CN6XXX_PCIE_CORR_ERR_STATUS 0x110
46 #define CN6XXX_PCIE_CORR_ERR_MASK 0x114
47 #define CN6XXX_PCIE_ADV_ERR_CAP 0x118
49 #define CN6XXX_PCIE_ACK_REPLAY_TIMER 0x700
50 #define CN6XXX_PCIE_OTHER_MSG 0x704
51 #define CN6XXX_PCIE_PORT_FORCE_LINK 0x708
52 #define CN6XXX_PCIE_ACK_FREQ 0x70C
53 #define CN6XXX_PCIE_PORT_LINK_CTL 0x710
54 #define CN6XXX_PCIE_LANE_SKEW 0x714
55 #define CN6XXX_PCIE_SYM_NUM 0x718
56 #define CN6XXX_PCIE_FLTMSK 0x720
60 #define CN6XXX_SLI_CTL_PORT0 0x0050
61 #define CN6XXX_SLI_CTL_PORT1 0x0060
63 #define CN6XXX_SLI_WINDOW_CTL 0x02E0
64 #define CN6XXX_SLI_DBG_DATA 0x0310
65 #define CN6XXX_SLI_SCRATCH1 0x03C0
66 #define CN6XXX_SLI_SCRATCH2 0x03D0
67 #define CN6XXX_SLI_CTL_STATUS 0x0570
69 #define CN6XXX_WIN_WR_ADDR_LO 0x0000
70 #define CN6XXX_WIN_WR_ADDR_HI 0x0004
73 #define CN6XXX_WIN_RD_ADDR_LO 0x0010
74 #define CN6XXX_WIN_RD_ADDR_HI 0x0014
77 #define CN6XXX_WIN_WR_DATA_LO 0x0020
78 #define CN6XXX_WIN_WR_DATA_HI 0x0024
81 #define CN6XXX_WIN_RD_DATA_LO 0x0040
82 #define CN6XXX_WIN_RD_DATA_HI 0x0044
85 #define CN6XXX_WIN_WR_MASK_LO 0x0030
86 #define CN6XXX_WIN_WR_MASK_HI 0x0034
90 #define CN6XXX_SLI_PKT_INSTR_ENB 0x1000
93 #define CN6XXX_SLI_PKT_OUT_ENB 0x1010
96 #define CN6XXX_SLI_PORT_IN_RST_OQ 0x11F0
99 #define CN6XXX_SLI_PORT_IN_RST_IQ 0x11F4
104 #define CN6XXX_SLI_PKT_INSTR_SIZE 0x1020
107 #define CN6XXX_SLI_IQ_INSTR_COUNT_START 0x2000
110 #define CN6XXX_SLI_IQ_BASE_ADDR_START64 0x2800
113 #define CN6XXX_SLI_IQ_DOORBELL_START 0x2C00
116 #define CN6XXX_SLI_IQ_SIZE_START 0x3000
119 #define CN6XXX_SLI_IQ_PKT_INSTR_HDR_START64 0x3400
122 #define CN66XX_SLI_INPUT_BP_START64 0x3800
125 #define CN6XXX_IQ_OFFSET 0x10
130 #define CN6XXX_SLI_PKT_INPUT_CONTROL 0x1170
135 #define CN6XXX_SLI_PKT_INSTR_RD_SIZE 0x11A0
140 #define CN6XXX_SLI_IN_PCIE_PORT 0x11B0
185 #define CN6XXX_SLI_OQ0_BUFF_INFO_SIZE 0x0C00
188 #define CN6XXX_SLI_OQ_BASE_ADDR_START64 0x1400
191 #define CN6XXX_SLI_OQ_PKT_CREDITS_START 0x1800
194 #define CN6XXX_SLI_OQ_SIZE_START 0x1C00
197 #define CN6XXX_SLI_OQ_PKT_SENT_START 0x2400
200 #define CN6XXX_OQ_OFFSET 0x10
206 #define CN6XXX_SLI_PKT_SLIST_ROR 0x1030
212 #define CN6XXX_SLI_PKT_SLIST_NS 0x1040
218 #define CN6XXX_SLI_PKT_SLIST_ES64 0x1050
224 #define CN6XXX_SLI_PKT_IPTR 0x1070
230 #define CN6XXX_SLI_PKT_DPADDR 0x1080
236 #define CN6XXX_SLI_PKT_DATA_OUT_ROR 0x1090
242 #define CN6XXX_SLI_PKT_DATA_OUT_NS 0x10A0
248 #define CN6XXX_SLI_PKT_DATA_OUT_ES64 0x10B0
254 #define CN6XXX_SLI_PKT_OUT_BMODE 0x10D0
260 #define CN6XXX_SLI_PKT_PCIE_PORT64 0x10E0
267 #define CN6XXX_SLI_OQ_INT_LEVEL_PKTS 0x1120
268 #define CN6XXX_SLI_OQ_INT_LEVEL_TIME 0x1124
271 #define CN6XXX_SLI_OQ_WMARK 0x1180
274 #define CN6XXX_SLI_PKT_CTL 0x1220
294 /* 2 registers (64-bit) - DMA Count - 1 for each DMA counter 0/1. */
295 #define CN6XXX_DMA_CNT_START 0x0400
297 /* 2 registers (64-bit) - DMA Timer 0/1, contains DMA timer values
300 #define CN6XXX_DMA_TIM_START 0x0420
305 #define CN6XXX_DMA_INT_LEVEL_START 0x03E0
308 #define CN6XXX_DMA_OFFSET 0x10
329 #define CN6XXX_SLI_INT_SUM64 0x0330
332 #define CN6XXX_SLI_INT_ENB64_PORT0 0x0340
333 #define CN6XXX_SLI_INT_ENB64_PORT1 0x0350
336 #define CN6XXX_SLI_PKT_CNT_INT_ENB 0x1150
339 #define CN6XXX_SLI_PKT_TIME_INT_ENB 0x1160
342 #define CN6XXX_SLI_PKT_CNT_INT 0x1130
345 #define CN6XXX_SLI_PKT_TIME_INT 0x1140
438 #define CN6XXX_SLI_S2M_PORT0_CTL 0x3D80
439 #define CN6XXX_SLI_S2M_PORT1_CTL 0x3D90
441 (CN6XXX_SLI_S2M_PORT0_CTL + ((port) * 0x10))
444 (CN6XXX_SLI_INT_ENB64_PORT0 + ((port) * 0x10))
446 #define CN6XXX_SLI_MAC_NUMBER 0x3E00
449 #define CN6XXX_PEM_BAR1_INDEX000 0x00011800C00000A8ULL
450 #define CN6XXX_PEM_OFFSET 0x0000000001000000ULL
453 #define CN6XXX_PCI_BAR1_OFFSET 0x8
461 #define CN6XXX_DPI_CTL 0x0001df0000000040ULL
463 #define CN6XXX_DPI_DMA_CONTROL 0x0001df0000000048ULL
465 #define CN6XXX_DPI_REQ_GBL_ENB 0x0001df0000000050ULL
467 #define CN6XXX_DPI_REQ_ERR_RSP 0x0001df0000000058ULL
469 #define CN6XXX_DPI_REQ_ERR_RST 0x0001df0000000060ULL
471 #define CN6XXX_DPI_DMA_ENG0_ENB 0x0001df0000000080ULL
476 #define CN6XXX_DPI_DMA_ENG0_BUF 0x0001df0000000880ULL
481 #define CN6XXX_DPI_SLI_PRT0_CFG 0x0001df0000000900ULL
482 #define CN6XXX_DPI_SLI_PRT1_CFG 0x0001df0000000908ULL
484 (CN6XXX_DPI_SLI_PRT0_CFG + ((port) * 0x10))
501 #define CN6XXX_CIU_SOFT_BIST 0x0001070000000738ULL
502 #define CN6XXX_CIU_SOFT_RST 0x0001070000000740ULL
505 #define CN6XXX_MIO_PTP_CLOCK_CFG 0x0001070000000f00ULL
506 #define CN6XXX_MIO_PTP_CLOCK_LO 0x0001070000000f08ULL
507 #define CN6XXX_MIO_PTP_CLOCK_HI 0x0001070000000f10ULL
508 #define CN6XXX_MIO_PTP_CLOCK_COMP 0x0001070000000f18ULL
509 #define CN6XXX_MIO_PTP_TIMESTAMP 0x0001070000000f20ULL
510 #define CN6XXX_MIO_PTP_EVT_CNT 0x0001070000000f28ULL
511 #define CN6XXX_MIO_PTP_CKOUT_THRESH_LO 0x0001070000000f30ULL
512 #define CN6XXX_MIO_PTP_CKOUT_THRESH_HI 0x0001070000000f38ULL
513 #define CN6XXX_MIO_PTP_CKOUT_HI_INCR 0x0001070000000f40ULL
514 #define CN6XXX_MIO_PTP_CKOUT_LO_INCR 0x0001070000000f48ULL
515 #define CN6XXX_MIO_PTP_PPS_THRESH_LO 0x0001070000000f50ULL
516 #define CN6XXX_MIO_PTP_PPS_THRESH_HI 0x0001070000000f58ULL
517 #define CN6XXX_MIO_PTP_PPS_HI_INCR 0x0001070000000f60ULL
518 #define CN6XXX_MIO_PTP_PPS_LO_INCR 0x0001070000000f68ULL
520 #define CN6XXX_MIO_QLM4_CFG 0x00011800000015B0ULL
521 #define CN6XXX_MIO_RST_BOOT 0x0001180000001600ULL
523 #define CN6XXX_MIO_QLM_CFG_MASK 0x7
527 #define CN6XXX_LMC0_RESET_CTL 0x0001180088000180ULL
528 #define CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK 0x0000000000000001ULL