24 #define RALINK_PCI_IO_MAP_BASE		0x10160000
25 #define RALINK_PCI_MEMORY_BASE		0x0
29 #define RALINK_CLKCFG1			0x30
30 #define RALINK_GPIOMODE			0x60
32 #define PPLL_CFG1			0x9c
35 #define PPLL_DRV			0xa0
43 #define RALINK_PCI_PCICFG_ADDR		0x00
46 #define RALINK_PCI_PCIENA		0x0C
49 #define RALINK_PCI_CONFIG_ADDR		0x20
50 #define RALINK_PCI_CONFIG_DATA_VIRT_REG	0x24
51 #define RALINK_PCI_MEMBASE		0x28
52 #define RALINK_PCI_IOBASE		0x2C
55 #define RALINK_PCI0_BAR0SETUP_ADDR	0x10
56 #define RALINK_PCI0_IMBASEBAR0_ADDR	0x18
57 #define RALINK_PCI0_ID			0x30
58 #define RALINK_PCI0_CLASS		0x34
59 #define RALINK_PCI0_SUBID		0x38
60 #define RALINK_PCI0_STATUS		0x50
61 #define PCIE_LINK_UP_ST			BIT(0)
63 #define PCIEPHY0_CFG			0x90
65 #define RALINK_PCIEPHY_P0_CTL_OFFSET	0x7498
68 #define BUSY				0x80000000
71 #define DATA_SHIFT			0
111 	unsigned long reg_value = 0x0, retry = 0;  in wait_pciephy_busy()
125 	return 0;  in wait_pciephy_busy()
144 	u32 num = 0;  in pci_config_read()
149 	address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |  in pci_config_read()
150 		  (func << 8) | (where & 0xfc) | 0x80000000;  in pci_config_read()
156 		*val = (data >> ((where & 3) << 3)) & 0xff;  in pci_config_read()
159 		*val = (data >> ((where & 3) << 3)) & 0xffff;  in pci_config_read()
176 	u32 num = 0;  in pci_config_write()
181 	address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |  in pci_config_write()
182 		  (func << 8) | (where & 0xfc) | 0x80000000;  in pci_config_write()
188 		data = (data & ~(0xff << ((where & 3) << 3))) |  in pci_config_write()
192 		data = (data & ~(0xffff << ((where & 3) << 3))) |  in pci_config_write()
215 	.mem_offset	= 0x00000000UL,
217 	.io_offset	= 0x00000000UL,
218 	.io_map_base	= 0xa0000000,
224 	pcie_phy(0x0, 0x80);  in mt7620_pci_hw_init()
225 	pcie_phy(0x1, 0x04);  in mt7620_pci_hw_init()
228 	pcie_phy(0x68, 0xB4);  in mt7620_pci_hw_init()
231 	pcie_m32(0, PCIRST, RALINK_PCI_PCICFG_ADDR);  in mt7620_pci_hw_init()
235 	rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);  in mt7620_pci_hw_init()
240 	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);  in mt7620_pci_hw_init()
246 		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);  in mt7620_pci_hw_init()
254 	return 0;  in mt7620_pci_hw_init()
259 	u32 val = 0;  in mt7628_pci_hw_init()
262 	rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);  in mt7628_pci_hw_init()
266 	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);  in mt7628_pci_hw_init()
270 	pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);  in mt7628_pci_hw_init()
272 	pci_config_read(NULL, 0, 0x70c, 4, &val);  in mt7628_pci_hw_init()
273 	val &= ~(0xff) << 8;  in mt7628_pci_hw_init()
274 	val |= 0x50 << 8;  in mt7628_pci_hw_init()
275 	pci_config_write(NULL, 0, 0x70c, 4, val);  in mt7628_pci_hw_init()
277 	return 0;  in mt7628_pci_hw_init()
282 	u32 val = 0;  in mt7620_pci_probe()
288 	bridge_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);  in mt7620_pci_probe()
296 	iomem_resource.start = 0;  in mt7620_pci_probe()
297 	iomem_resource.end = ~0;  in mt7620_pci_probe()
298 	ioport_resource.start = 0;  in mt7620_pci_probe()
299 	ioport_resource.end = ~0;  in mt7620_pci_probe()
321 	pcie_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);  in mt7620_pci_probe()
325 	if ((pcie_r32(RALINK_PCI0_STATUS) & PCIE_LINK_UP_ST) == 0) {  in mt7620_pci_probe()
327 		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);  in mt7620_pci_probe()
335 	bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);  in mt7620_pci_probe()
338 	pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);  in mt7620_pci_probe()
340 	pcie_w32(0x06040001, RALINK_PCI0_CLASS);  in mt7620_pci_probe()
343 	pcie_m32(0, PCIINT2, RALINK_PCI_PCIENA);  in mt7620_pci_probe()
346 	pci_config_read(NULL, 0, 4, 4, &val);  in mt7620_pci_probe()
347 	pci_config_write(NULL, 0, 4, 4, val | 0x7);  in mt7620_pci_probe()
352 	return 0;  in mt7620_pci_probe()
359 	int irq = 0;  in pcibios_map_irq()
361 	if ((dev->bus->number == 0) && (slot == 0)) {  in pcibios_map_irq()
362 		pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);  in pcibios_map_irq()
363 		pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,  in pcibios_map_irq()
365 		pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);  in pcibios_map_irq()
366 	} else if ((dev->bus->number == 1) && (slot == 0x0)) {  in pcibios_map_irq()
369 		dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n",  in pcibios_map_irq()
371 		return 0;  in pcibios_map_irq()
373 	dev_info(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",  in pcibios_map_irq()
376 	/* configure the cache line size to 0x14 */  in pcibios_map_irq()
377 	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  in pcibios_map_irq()
379 	/* configure latency timer to 0xff */  in pcibios_map_irq()
380 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xff);  in pcibios_map_irq()
393 	return 0;  in pcibios_plat_dev_init()