Lines Matching +full:0 +full:x70c

16 #define EXYNOS_5250_REFCLKSEL_CRYSTAL	0x0
17 #define EXYNOS_5250_REFCLKSEL_XO	0x1
18 #define EXYNOS_5250_REFCLKSEL_CLKCORE	0x2
20 #define EXYNOS_5250_FSEL_9MHZ6		0x0
21 #define EXYNOS_5250_FSEL_10MHZ		0x1
22 #define EXYNOS_5250_FSEL_12MHZ		0x2
23 #define EXYNOS_5250_FSEL_19MHZ2		0x3
24 #define EXYNOS_5250_FSEL_20MHZ		0x4
25 #define EXYNOS_5250_FSEL_24MHZ		0x5
26 #define EXYNOS_5250_FSEL_50MHZ		0x7
29 #define EXYNOS_5250_HOSTPHYCTRL0			0x0
34 		(0x3 << EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT)
37 		(0x7 << EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT)
41 #define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_MASK		(0x3 << 7)
42 #define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_DUAL		(0x0 << 7)
43 #define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ID0		(0x1 << 7)
44 #define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ANALOGTEST	(0x2 << 7)
51 #define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST		BIT(0)
54 #define EXYNOS_5250_HSICPHYCTRL1			0x10
55 #define EXYNOS_5250_HSICPHYCTRL2			0x20
57 #define EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_MASK		(0x3 << 23)
58 #define EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_DEFAULT	(0x2 << 23)
59 #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_MASK		(0x7f << 16)
60 #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_12		(0x24 << 16)
61 #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_15		(0x1c << 16)
62 #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_16		(0x1a << 16)
63 #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_19_2		(0x15 << 16)
64 #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_20		(0x14 << 16)
70 #define EXYNOS_5250_HSICPHYCTRLX_PHYSWRST		BIT(0)
73 #define EXYNOS_5250_HOSTEHCICTRL			0x30
81 		(0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT)
84 		(0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_SHIFT)
87 		(0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT)
90 		(0x1 << EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_SHIFT)
91 #define EXYNOS_5250_HOSTEHCICTRL_SIMULATIONMODE		BIT(0)
94 #define EXYNOS_5250_HOSTOHCICTRL                        0x34
97 		(0x3ff << EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_SHIFT)
98 #define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVALEN		BIT(0)
101 #define EXYNOS_5250_USBOTGSYS				0x38
107 		(0x3 << EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT)
112 		(0x3 << EXYNOS_5250_USBOTGSYS_FSEL_SHIFT)
116 #define EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND		BIT(0)
119 #define EXYNOS_5250_USB_ISOL_OTG_OFFSET		0x704
120 #define EXYNOS_5250_USB_ISOL_HOST_OFFSET	0x708
121 #define EXYNOS_5420_USB_ISOL_HOST_OFFSET	0x70C
122 #define EXYNOS_5250_USB_ISOL_ENABLE		BIT(0)
125 #define EXYNOS_5250_MODE_SWITCH_OFFSET		0x230
127 #define EXYNOS_5250_MODE_SWITCH_DEVICE		0
171 	return 0;  in exynos5250_rate_to_clk()
192 	regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);  in exynos5250_isol()
311 		ohci |=	0x1 << 3;  in exynos5250_power_on()
316 	exynos5250_isol(inst, 0);  in exynos5250_power_on()
318 	return 0;  in exynos5250_power_on()
360 	return 0;  in exynos5250_power_off()