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/linux-6.12.1/Documentation/devicetree/bindings/dma/
Dmarvell,xor-v2.yaml56 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
57 clocks = <&ap_clk 0>, <&ap_clk 1>;
/linux-6.12.1/drivers/net/ethernet/cavium/thunder/
Dnic_reg.h13 #define NIC_PF_CFG (0x0000)
14 #define NIC_PF_STATUS (0x0010)
15 #define NIC_PF_INTR_TIMER_CFG (0x0030)
16 #define NIC_PF_BIST_STATUS (0x0040)
17 #define NIC_PF_SOFT_RESET (0x0050)
18 #define NIC_PF_TCP_TIMER (0x0060)
19 #define NIC_PF_BP_CFG (0x0080)
20 #define NIC_PF_RRM_CFG (0x0088)
21 #define NIC_PF_CQM_CFG (0x00A0)
22 #define NIC_PF_CNM_CF (0x00A8)
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Domap3-cm-t3x.dtsi10 reg = <0x80000000 0x10000000>; /* 256 MB */
16 pinctrl-0 = <&green_led_pins>;
46 #phy-cells = <0>;
53 #phy-cells = <0>;
79 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
80 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
86 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
87 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
88 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
89 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-j721e-som-p0.dtsi17 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
18 <0x00000008 0x80000000 0x00000000 0x80000000>;
27 reg = <0x00 0x9e800000 0x00 0x01800000>;
28 alignment = <0x1000>;
34 reg = <0x00 0xa0000000 0x00 0x100000>;
40 reg = <0x00 0xa0100000 0x00 0xf00000>;
46 reg = <0x00 0xa1000000 0x00 0x100000>;
52 reg = <0x00 0xa1100000 0x00 0xf00000>;
58 reg = <0x00 0xa2000000 0x00 0x100000>;
64 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
Dk3-am654-base-board.dts38 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
39 <0x00000008 0x80000000 0x00000000 0x80000000>;
48 reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
49 alignment = <0x1000>;
55 reg = <0 0xa0000000 0 0x100000>;
61 reg = <0 0xa0100000 0 0xf00000>;
67 reg = <0 0xa1000000 0 0x100000>;
73 reg = <0 0xa1100000 0 0xf00000>;
78 reg = <0x00 0xa2000000 0x00 0x00100000>;
79 alignment = <0x1000>;
[all …]
Dk3-am65-iot2050-common.dtsi45 reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
46 alignment = <0x1000>;
52 reg = <0 0xa0000000 0 0x100000>;
58 reg = <0 0xa0100000 0 0xf00000>;
64 reg = <0 0xa1000000 0 0x100000>;
70 reg = <0 0xa1100000 0 0xf00000>;
75 reg = <0x00 0xa2000000 0x00 0x00200000>;
76 alignment = <0x1000>;
82 reg = <0x00 0xa2200000 0x00 0x1000>;
90 pinctrl-0 = <&leds_pins_default>;
[all …]
Dk3-j721e-common-proc-board.dts40 pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>;
45 gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
101 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
108 states = <1800000 0x0>,
109 <3300000 0x1>;
112 sound0: sound-0 {
131 #phy-cells = <0>;
134 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
136 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
141 #phy-cells = <0>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/marvell/
Darmada-cp11x.dtsi29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
58 ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
60 CP11X_LABEL(ethernet): ethernet@0 {
62 #size-cells = <0>;
64 reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
74 CP11X_LABEL(eth0): ethernet-port@0 {
88 reg = <0>;
89 port-id = <0>; /* For backward compatibility. */
[all …]
/linux-6.12.1/drivers/scsi/pm8001/
Dpm8001_hwi.h48 #define OPC_INB_ECHO 1 /* 0x000 */
49 #define OPC_INB_PHYSTART 4 /* 0x004 */
50 #define OPC_INB_PHYSTOP 5 /* 0x005 */
51 #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
52 #define OPC_INB_SSPINITMSTART 7 /* 0x007 */
53 #define OPC_INB_SSPINIEXTIOSTART 8 /* 0x008 */
54 #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
55 #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
56 #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
57 #define OPC_INB_SSPINIEDCIOSTART 12 /* 0x00C */
[all …]
Dpm80xx_hwi.h48 #define OPC_INB_ECHO 1 /* 0x000 */
49 #define OPC_INB_PHYSTART 4 /* 0x004 */
50 #define OPC_INB_PHYSTOP 5 /* 0x005 */
51 #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
52 #define OPC_INB_SSPINITMSTART 7 /* 0x007 */
53 /* 0x8 RESV IN SPCv */
54 #define OPC_INB_RSVD 8 /* 0x008 */
55 #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
56 #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
57 #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
[all …]