Lines Matching +full:0 +full:x6a0000
48 #define OPC_INB_ECHO 1 /* 0x000 */
49 #define OPC_INB_PHYSTART 4 /* 0x004 */
50 #define OPC_INB_PHYSTOP 5 /* 0x005 */
51 #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
52 #define OPC_INB_SSPINITMSTART 7 /* 0x007 */
53 #define OPC_INB_SSPINIEXTIOSTART 8 /* 0x008 */
54 #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
55 #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
56 #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
57 #define OPC_INB_SSPINIEDCIOSTART 12 /* 0x00C */
58 #define OPC_INB_SSPINIEXTEDCIOSTART 13 /* 0x00D */
59 #define OPC_INB_SSPTGTEDCIOSTART 14 /* 0x00E */
60 #define OPC_INB_SSP_ABORT 15 /* 0x00F */
61 #define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */
62 #define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */
63 #define OPC_INB_SMP_REQUEST 18 /* 0x012 */
65 #define OPC_INB_SMP_RESPONSE 19 /* 0x013 */
66 #define OPC_INB_SMP_ABORT 20 /* 0x014 */
67 #define OPC_INB_REG_DEV 22 /* 0x016 */
68 #define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */
69 #define OPC_INB_SATA_ABORT 24 /* 0x018 */
70 #define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */
71 #define OPC_INB_GET_DEV_INFO 26 /* 0x01A */
72 #define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */
73 #define OPC_INB_GPIO 34 /* 0x022 */
74 #define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */
75 #define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */
76 #define OPC_INB_SAS_HW_EVENT_ACK 37 /* 0x025 */
77 #define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */
78 #define OPC_INB_PORT_CONTROL 39 /* 0x027 */
79 #define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */
80 #define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */
81 #define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */
82 #define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */
83 #define OPC_INB_SET_DEV_INFO 44 /* 0x02C */
84 #define OPC_INB_SAS_RE_INITIALIZE 45 /* 0x02D */
87 #define OPC_OUB_ECHO 1 /* 0x001 */
88 #define OPC_OUB_HW_EVENT 4 /* 0x004 */
89 #define OPC_OUB_SSP_COMP 5 /* 0x005 */
90 #define OPC_OUB_SMP_COMP 6 /* 0x006 */
91 #define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */
92 #define OPC_OUB_DEV_REGIST 10 /* 0x00A */
93 #define OPC_OUB_DEREG_DEV 11 /* 0x00B */
94 #define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */
95 #define OPC_OUB_SATA_COMP 13 /* 0x00D */
96 #define OPC_OUB_SATA_EVENT 14 /* 0x00E */
97 #define OPC_OUB_SSP_EVENT 15 /* 0x00F */
98 #define OPC_OUB_DEV_HANDLE_ARRIV 16 /* 0x010 */
100 #define OPC_OUB_SMP_RECV_EVENT 17 /* 0x011 */
101 #define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */
102 #define OPC_OUB_DEV_INFO 19 /* 0x013 */
103 #define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */
104 #define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */
105 #define OPC_OUB_GPIO_EVENT 23 /* 0x017 */
106 #define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */
107 #define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */
108 #define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */
109 #define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */
110 #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
111 #define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */
112 #define OPC_OUB_SAS_HW_EVENT_ACK 31 /* 0x01F */
113 #define OPC_OUB_PORT_CONTROL 32 /* 0x020 */
114 #define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */
115 #define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */
116 #define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */
117 #define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */
118 #define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */
119 #define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */
120 #define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */
121 #define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */
122 #define OPC_OUB_SAS_RE_INITIALIZE 41 /* 0x029 */
125 #define SPINHOLD_DISABLE (0x00 << 14)
126 #define SPINHOLD_ENABLE (0x01 << 14)
127 #define LINKMODE_SAS (0x01 << 12)
128 #define LINKMODE_DSATA (0x02 << 12)
129 #define LINKMODE_AUTO (0x03 << 12)
130 #define LINKRATE_15 (0x01 << 8)
131 #define LINKRATE_30 (0x02 << 8)
132 #define LINKRATE_60 (0x04 << 8)
135 #define GSM_SM_BASE 0x4F0000
137 __le32 header; /* Bits [11:0] - Message operation code */
174 u8 fis_type; /* 0xA1*/
186 u8 fis_type; /* 0x5f */
302 #define OP_BITS 0x0000FF00
303 #define ID_BITS 0x000000FF
347 #define SSP_RESCV_BIT 0x00010000
386 #define OPCODE_BITS 0x00000fff
396 /* Bits [0] - Indirect response */
498 ** bit26-set open reject option, remap:1 or not:0.
549 /* B2-0 : taskAttribute */
553 /* B1-0 : reserved */
592 #define FWFLASH_IOMB_RESERVED_LEN 0x07
633 #define TWI_DEVICE 0x0
634 #define C_SEEPROM 0x1
635 #define VPD_FLASH 0x4
636 #define AAP1_RDUMP 0x5
637 #define IOP_RDUMP 0x6
638 #define EXPAN_ROM 0x7
640 #define IPMode 0x80000000
641 #define NVMD_TYPE 0x0000000F
642 #define NVMD_STAT 0x0000FFFF
643 #define NVMD_LEN 0xFF000000
696 #define NDS_BITS 0x0F
697 #define PDS_BITS 0xF0
703 #define HW_EVENT_RESET_START 0x01
704 #define HW_EVENT_CHIP_RESET_COMPLETE 0x02
705 #define HW_EVENT_PHY_STOP_STATUS 0x03
706 #define HW_EVENT_SAS_PHY_UP 0x04
707 #define HW_EVENT_SATA_PHY_UP 0x05
708 #define HW_EVENT_SATA_SPINUP_HOLD 0x06
709 #define HW_EVENT_PHY_DOWN 0x07
710 #define HW_EVENT_PORT_INVALID 0x08
711 #define HW_EVENT_BROADCAST_CHANGE 0x09
712 #define HW_EVENT_PHY_ERROR 0x0A
713 #define HW_EVENT_BROADCAST_SES 0x0B
714 #define HW_EVENT_INBOUND_CRC_ERROR 0x0C
715 #define HW_EVENT_HARD_RESET_RECEIVED 0x0D
716 #define HW_EVENT_MALFUNCTION 0x0E
717 #define HW_EVENT_ID_FRAME_TIMEOUT 0x0F
718 #define HW_EVENT_BROADCAST_EXP 0x10
719 #define HW_EVENT_PHY_START_STATUS 0x11
720 #define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12
721 #define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13
722 #define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14
723 #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15
724 #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16
725 #define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
726 #define HW_EVENT_PORT_RECOVER 0x18
727 #define HW_EVENT_PORT_RESET_TIMER_TMO 0x19
728 #define HW_EVENT_PORT_RESET_COMPLETE 0x20
729 #define EVENT_BROADCAST_ASYNCH_EVENT 0x21
732 #define PORT_NOT_ESTABLISHED 0x00
733 #define PORT_VALID 0x01
734 #define PORT_LOSTCOMM 0x02
735 #define PORT_IN_RESET 0x04
736 #define PORT_INVALID 0x08
742 #define IO_SUCCESS 0x00
743 #define IO_ABORTED 0x01
744 #define IO_OVERFLOW 0x02
745 #define IO_UNDERFLOW 0x03
746 #define IO_FAILED 0x04
747 #define IO_ABORT_RESET 0x05
748 #define IO_NOT_VALID 0x06
749 #define IO_NO_DEVICE 0x07
750 #define IO_ILLEGAL_PARAMETER 0x08
751 #define IO_LINK_FAILURE 0x09
752 #define IO_PROG_ERROR 0x0A
753 #define IO_EDC_IN_ERROR 0x0B
754 #define IO_EDC_OUT_ERROR 0x0C
755 #define IO_ERROR_HW_TIMEOUT 0x0D
756 #define IO_XFER_ERROR_BREAK 0x0E
757 #define IO_XFER_ERROR_PHY_NOT_READY 0x0F
758 #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10
759 #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
760 #define IO_OPEN_CNX_ERROR_BREAK 0x12
761 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
762 #define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14
763 #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
764 #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
765 #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
766 #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
767 #define IO_XFER_ERROR_NAK_RECEIVED 0x19
768 #define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
769 #define IO_XFER_ERROR_PEER_ABORTED 0x1B
770 #define IO_XFER_ERROR_RX_FRAME 0x1C
771 #define IO_XFER_ERROR_DMA 0x1D
772 #define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E
773 #define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
774 #define IO_XFER_ERROR_SATA 0x20
775 #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
776 #define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21
777 #define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23
778 #define IO_XFER_OPEN_RETRY_TIMEOUT 0x24
779 #define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25
780 #define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26
781 #define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27
782 #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28
784 #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
785 #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31
786 #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
788 #define IO_XFER_ERROR_OFFSET_MISMATCH 0x34
789 #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35
790 #define IO_XFER_CMD_FRAME_ISSUED 0x36
791 #define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37
792 #define IO_PORT_IN_RESET 0x38
793 #define IO_DS_NON_OPERATIONAL 0x39
794 #define IO_DS_IN_RECOVERY 0x3A
795 #define IO_TM_TAG_NOT_FOUND 0x3B
796 #define IO_XFER_PIO_SETUP_ERROR 0x3C
797 #define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
798 #define IO_DS_IN_ERROR 0x3E
799 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
800 #define IO_ABORT_IN_PROGRESS 0x40
801 #define IO_ABORT_DELAYED 0x41
802 #define IO_INVALID_LENGTH 0x42
803 #define IO_FATAL_ERROR 0x51
809 #define IO_ERROR_UNKNOWN_GENERIC 0x43
813 #define SPC_MSGU_CFG_TABLE_UPDATE 0x01/* Inbound doorbell bit0 */
814 #define SPC_MSGU_CFG_TABLE_RESET 0x02/* Inbound doorbell bit1 */
815 #define SPC_MSGU_CFG_TABLE_FREEZE 0x04/* Inbound doorbell bit2 */
816 #define SPC_MSGU_CFG_TABLE_UNFREEZE 0x08/* Inbound doorbell bit4 */
817 #define MSGU_IBDB_SET 0x04
818 #define MSGU_HOST_INT_STATUS 0x08
819 #define MSGU_HOST_INT_MASK 0x0C
820 #define MSGU_IOPIB_INT_STATUS 0x18
821 #define MSGU_IOPIB_INT_MASK 0x1C
822 #define MSGU_IBDB_CLEAR 0x20/* RevB - Host not use */
823 #define MSGU_MSGU_CONTROL 0x24
824 #define MSGU_ODR 0x3C/* RevB */
825 #define MSGU_ODCR 0x40/* RevB */
826 #define MSGU_SCRATCH_PAD_0 0x44
827 #define MSGU_SCRATCH_PAD_1 0x48
828 #define MSGU_SCRATCH_PAD_2 0x4C
829 #define MSGU_SCRATCH_PAD_3 0x50
830 #define MSGU_HOST_SCRATCH_PAD_0 0x54
831 #define MSGU_HOST_SCRATCH_PAD_1 0x58
832 #define MSGU_HOST_SCRATCH_PAD_2 0x5C
833 #define MSGU_HOST_SCRATCH_PAD_3 0x60
834 #define MSGU_HOST_SCRATCH_PAD_4 0x64
835 #define MSGU_HOST_SCRATCH_PAD_5 0x68
836 #define MSGU_HOST_SCRATCH_PAD_6 0x6C
837 #define MSGU_HOST_SCRATCH_PAD_7 0x70
838 #define MSGU_ODMR 0x74/* RevB */
841 #define ODMR_MASK_ALL 0xFFFFFFFF/* mask all
843 #define ODMR_CLEAR_ALL 0/* clear all
846 #define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all
849 #define MSIX_TABLE_OFFSET 0x2000
850 #define MSIX_TABLE_ELEMENT_SIZE 0x10
851 #define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
853 #define MSIX_INTERRUPT_DISABLE 0x1
854 #define MSIX_INTERRUPT_ENABLE 0x0
858 #define SCRATCH_PAD1_POR 0x00 /* power on reset state */
859 #define SCRATCH_PAD1_SFR 0x01 /* soft reset state */
860 #define SCRATCH_PAD1_ERR 0x02 /* error state */
861 #define SCRATCH_PAD1_RDY 0x03 /* ready state */
862 #define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */
863 #define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */
864 #define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1
865 Mask, bit1-0 State, bit2 Soft Reset, bit3 FW RDY for Soft Reset */
866 #define SCRATCH_PAD1_RESERVED 0x000003F8 /* Scratch Pad1
870 #define SCRATCH_PAD2_POR 0x00 /* power on state */
871 #define SCRATCH_PAD2_SFR 0x01 /* soft reset state */
872 #define SCRATCH_PAD2_ERR 0x02 /* error state */
873 #define SCRATCH_PAD2_RDY 0x03 /* ready state */
874 #define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset flag*/
875 #define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */
876 #define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2
877 Mask, bit1-0 State */
878 #define SCRATCH_PAD2_RESERVED 0x000003FC /* Scratch Pad1
881 #define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */
882 #define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */
885 #define MAIN_SIGNATURE_OFFSET 0x00/* DWORD 0x00 */
886 #define MAIN_INTERFACE_REVISION 0x04/* DWORD 0x01 */
887 #define MAIN_FW_REVISION 0x08/* DWORD 0x02 */
888 #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C/* DWORD 0x03 */
889 #define MAIN_MAX_SGL_OFFSET 0x10/* DWORD 0x04 */
890 #define MAIN_CNTRL_CAP_OFFSET 0x14/* DWORD 0x05 */
891 #define MAIN_GST_OFFSET 0x18/* DWORD 0x06 */
892 #define MAIN_IBQ_OFFSET 0x1C/* DWORD 0x07 */
893 #define MAIN_OBQ_OFFSET 0x20/* DWORD 0x08 */
894 #define MAIN_IQNPPD_HPPD_OFFSET 0x24/* DWORD 0x09 */
895 #define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28/* DWORD 0x0A */
896 #define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C/* DWORD 0x0B */
897 #define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30/* DWORD 0x0C */
898 #define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34/* DWORD 0x0D */
899 #define MAIN_TITNX_EVENT_PID03_OFFSET 0x38/* DWORD 0x0E */
900 #define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C/* DWORD 0x0F */
901 #define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40/* DWORD 0x10 */
902 #define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44/* DWORD 0x11 */
903 #define MAIN_OB_SMP_EVENT_PID03_OFFSET 0x48/* DWORD 0x12 */
904 #define MAIN_OB_SMP_EVENT_PID47_OFFSET 0x4C/* DWORD 0x13 */
905 #define MAIN_EVENT_LOG_ADDR_HI 0x50/* DWORD 0x14 */
906 #define MAIN_EVENT_LOG_ADDR_LO 0x54/* DWORD 0x15 */
907 #define MAIN_EVENT_LOG_BUFF_SIZE 0x58/* DWORD 0x16 */
908 #define MAIN_EVENT_LOG_OPTION 0x5C/* DWORD 0x17 */
909 #define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60/* DWORD 0x18 */
910 #define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64/* DWORD 0x19 */
911 #define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68/* DWORD 0x1A */
912 #define MAIN_IOP_EVENT_LOG_OPTION 0x6C/* DWORD 0x1B */
913 #define MAIN_FATAL_ERROR_INTERRUPT 0x70/* DWORD 0x1C */
914 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74/* DWORD 0x1D */
915 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78/* DWORD 0x1E */
916 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C/* DWORD 0x1F */
917 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80/* DWORD 0x20 */
918 #define MAIN_HDA_FLAGS_OFFSET 0x84/* DWORD 0x21 */
919 #define MAIN_ANALOG_SETUP_OFFSET 0x88/* DWORD 0x22 */
922 #define GST_GSTLEN_MPIS_OFFSET 0x00
923 #define GST_IQ_FREEZE_STATE0_OFFSET 0x04
924 #define GST_IQ_FREEZE_STATE1_OFFSET 0x08
925 #define GST_MSGUTCNT_OFFSET 0x0C
926 #define GST_IOPTCNT_OFFSET 0x10
927 #define GST_PHYSTATE_OFFSET 0x18
928 #define GST_PHYSTATE0_OFFSET 0x18
929 #define GST_PHYSTATE1_OFFSET 0x1C
930 #define GST_PHYSTATE2_OFFSET 0x20
931 #define GST_PHYSTATE3_OFFSET 0x24
932 #define GST_PHYSTATE4_OFFSET 0x28
933 #define GST_PHYSTATE5_OFFSET 0x2C
934 #define GST_PHYSTATE6_OFFSET 0x30
935 #define GST_PHYSTATE7_OFFSET 0x34
936 #define GST_RERRINFO_OFFSET 0x44
939 #define GST_MPI_STATE_UNINIT 0x00
940 #define GST_MPI_STATE_INIT 0x01
941 #define GST_MPI_STATE_TERMINATION 0x02
942 #define GST_MPI_STATE_ERROR 0x03
943 #define GST_MPI_STATE_MASK 0x07
945 #define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
946 #define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
947 /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
948 #define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
949 #define PCIE_EVENT_INTERRUPT 0x003044
950 #define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
951 #define PCIE_ERROR_INTERRUPT 0x00304C
953 #define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
956 /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
957 #define SPC_REG_RESET 0x000000/* reset register */
960 #define SPC_REG_RESET_OSSP 0x00000001
961 #define SPC_REG_RESET_RAAE 0x00000002
962 #define SPC_REG_RESET_PCS_SPBC 0x00000004
963 #define SPC_REG_RESET_PCS_IOP_SS 0x00000008
964 #define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
965 #define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
966 #define SPC_REG_RESET_PCS_LM 0x00000040
967 #define SPC_REG_RESET_PCS 0x00000080
968 #define SPC_REG_RESET_GSM 0x00000100
969 #define SPC_REG_RESET_DDR2 0x00010000
970 #define SPC_REG_RESET_BDMA_CORE 0x00020000
971 #define SPC_REG_RESET_BDMA_SXCBI 0x00040000
972 #define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
973 #define SPC_REG_RESET_PCIE_PWR 0x00100000
974 #define SPC_REG_RESET_PCIE_SFT 0x00200000
975 #define SPC_REG_RESET_PCS_SXCBI 0x00400000
976 #define SPC_REG_RESET_LMS_SXCBI 0x00800000
977 #define SPC_REG_RESET_PMIC_SXCBI 0x01000000
978 #define SPC_REG_RESET_PMIC_CORE 0x02000000
979 #define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
980 #define SPC_REG_RESET_DEVICE 0x80000000
982 /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
983 #define SPC_IBW_AXI_TRANSLATION_LOW 0x003258
985 #define MBIC_AAP1_ADDR_BASE 0x060000
986 #define MBIC_IOP_ADDR_BASE 0x070000
987 #define GSM_ADDR_BASE 0x0700000
988 /* Dynamic map through Bar4 - 0x00700000 */
989 #define GSM_CONFIG_RESET 0x00000000
990 #define RAM_ECC_DB_ERR 0x00000018
991 #define GSM_READ_ADDR_PARITY_INDIC 0x00000058
992 #define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
993 #define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
994 #define GSM_READ_ADDR_PARITY_CHECK 0x00000038
995 #define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
996 #define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
998 #define RB6_ACCESS_REG 0x6A0000
999 #define HDAC_EXEC_CMD 0x0002
1000 #define HDA_C_PA 0xcb
1001 #define HDA_SEQ_ID_BITS 0x00ff0000
1002 #define HDA_GSM_OFFSET_BITS 0x00FFFFFF
1003 #define MBIC_AAP1_ADDR_BASE 0x060000
1004 #define MBIC_IOP_ADDR_BASE 0x070000
1005 #define GSM_ADDR_BASE 0x0700000
1006 #define SPC_TOP_LEVEL_ADDR_BASE 0x000000
1007 #define GSM_CONFIG_RESET_VALUE 0x00003b00
1008 #define GPIO_ADDR_BASE 0x00090000
1009 #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
1012 #define SPC_RB6_OFFSET 0x80C0
1014 #define RB6_MAGIC_NUMBER_RST 0x1234
1017 #define DEVREG_SUCCESS 0x00
1018 #define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01
1019 #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
1020 #define DEVREG_FAILURE_INVALID_PHY_ID 0x03
1021 #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
1022 #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
1023 #define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
1024 #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
1026 #define GSM_BASE 0x4F0000
1027 #define SHIFT_REG_64K_MASK 0xffff0000