Lines Matching +full:0 +full:x6a0000
40 pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>;
45 gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
101 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
108 states = <1800000 0x0>,
109 <3300000 0x1>;
112 sound0: sound-0 {
131 #phy-cells = <0>;
134 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
136 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
141 #phy-cells = <0>;
144 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
150 #phy-cells = <0>;
158 #phy-cells = <0>;
161 pinctrl-0 = <&main_mcan2_gpio_pins_default>;
170 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */
191 J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */
192 J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
193 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
194 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
200 J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */
201 J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */
207 J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */
208 J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */
214 J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */
215 J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */
221 J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
227 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
228 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
229 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
230 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
231 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
232 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
233 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
234 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
235 J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
241 J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
247 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
248 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
254 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
260 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
266 J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
272 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
273 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
279 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
280 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
286 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
287 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
293 J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
294 J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
300 J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
301 J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
302 J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
303 J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
304 J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
305 J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
306 J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
307 J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
308 J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
314 J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
320 J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
321 J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
327 J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */
328 J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */
334 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
342 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
343 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
349 J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */
350 J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
351 J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
352 J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
358 J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
364 J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
365 J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
366 J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
367 J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
368 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
369 J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
370 J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
371 J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
377 J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
378 J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
379 J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
380 J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
381 J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
382 J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
383 J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
384 J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
385 J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
386 J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
387 J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
388 J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
394 J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
395 J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
401 J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
402 J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
408 J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */
409 J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
415 J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
416 J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
422 J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
428 J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
437 pinctrl-0 = <&wkup_uart0_pins_default>;
443 pinctrl-0 = <&mcu_uart0_pins_default>;
449 pinctrl-0 = <&main_uart0_pins_default>;
457 pinctrl-0 = <&main_uart1_pins_default>;
463 pinctrl-0 = <&main_uart2_pins_default>;
469 pinctrl-0 = <&main_uart4_pins_default>;
475 pinctrl-0 = <&wkup_gpio_pins_default>;
500 pinctrl-0 = <&main_mmc1_pins_default>;
506 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
524 serdes3_usb_link: phy@0 {
525 reg = <0>;
527 #phy-cells = <0>;
535 pinctrl-0 = <&main_usbss0_pins_default>;
548 pinctrl-0 = <&main_usbss1_pins_default>;
559 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
561 flash@0 {
563 reg = <0x0>;
578 partition@0 {
580 reg = <0x0 0x80000>;
585 reg = <0x80000 0x200000>;
590 reg = <0x280000 0x400000>;
595 reg = <0x680000 0x20000>;
600 reg = <0x6a0000 0x20000>;
605 reg = <0x6c0000 0x100000>;
610 reg = <0x800000 0x37c0000>;
615 reg = <0x3fe0000 0x20000>;
624 ti,adc-channels = <0 1 2 3 4 5 6 7>;
631 ti,adc-channels = <0 1 2 3 4 5 6 7>;
638 pinctrl-0 = <&main_i2c0_pins_default>;
643 reg = <0x20>;
650 reg = <0x22>;
675 pinctrl-0 = <&main_i2c1_pins_default>;
680 reg = <0x20>;
684 pinctrl-0 = <&main_i2c1_exp4_pins_default>;
695 pinctrl-0 = <&audi_ext_refclk2_pins_default>;
701 pinctrl-0 = <&main_i2c3_pins_default>;
706 reg = <0x20>;
713 reg = <0x44>;
717 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
740 pinctrl-0 = <&main_i2c6_pins_default>;
745 reg = <0x20>;
753 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
757 phy0: ethernet-phy@0 {
758 reg = <0>;
799 #size-cells = <0>;
801 port@0 {
802 reg = <0>;
818 #sound-dai-cells = <0>;
821 pinctrl-0 = <&mcasp10_pins_default>;
823 op-mode = <0>; /* MCASP_IIS_MODE */
827 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
829 2 2 2 0
831 tx-num-evt = <0>;
832 rx-num-evt = <0>;
873 serdes0_pcie_link: phy@0 {
874 reg = <0>;
876 #phy-cells = <0>;
886 serdes1_pcie_link: phy@0 {
887 reg = <0>;
889 #phy-cells = <0>;
899 serdes2_pcie_link: phy@0 {
900 reg = <0>;
902 #phy-cells = <0>;
909 torrent_phy_dp: phy@0 {
910 reg = <0>;
915 #phy-cells = <0>;
923 pinctrl-0 = <&dp0_pins_default>;
953 pinctrl-0 = <&mcu_mcan0_pins_default>;
960 pinctrl-0 = <&mcu_mcan1_pins_default>;
967 pinctrl-0 = <&main_mcan0_pins_default>;
974 pinctrl-0 = <&main_mcan2_pins_default>;