Lines Matching +full:0 +full:x6a0000
48 #define OPC_INB_ECHO 1 /* 0x000 */
49 #define OPC_INB_PHYSTART 4 /* 0x004 */
50 #define OPC_INB_PHYSTOP 5 /* 0x005 */
51 #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
52 #define OPC_INB_SSPINITMSTART 7 /* 0x007 */
53 /* 0x8 RESV IN SPCv */
54 #define OPC_INB_RSVD 8 /* 0x008 */
55 #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
56 #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
57 #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
58 /* 0xC, 0xD, 0xE removed in SPCv */
59 #define OPC_INB_SSP_ABORT 15 /* 0x00F */
60 #define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */
61 #define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */
62 #define OPC_INB_SMP_REQUEST 18 /* 0x012 */
63 /* 0x13 SMP_RESPONSE is removed in SPCv */
64 #define OPC_INB_SMP_ABORT 20 /* 0x014 */
65 /* 0x16 RESV IN SPCv */
66 #define OPC_INB_RSVD1 22 /* 0x016 */
67 #define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */
68 #define OPC_INB_SATA_ABORT 24 /* 0x018 */
69 #define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */
70 /* 0x1A RESV IN SPCv */
71 #define OPC_INB_RSVD2 26 /* 0x01A */
72 #define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */
73 #define OPC_INB_GPIO 34 /* 0x022 */
74 #define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */
75 #define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */
76 /* 0x25 RESV IN SPCv */
77 #define OPC_INB_RSVD3 37 /* 0x025 */
78 #define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */
79 #define OPC_INB_PORT_CONTROL 39 /* 0x027 */
80 #define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */
81 #define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */
82 #define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */
83 #define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */
84 #define OPC_INB_SET_DEV_INFO 44 /* 0x02C */
85 /* 0x2D RESV IN SPCv */
86 #define OPC_INB_RSVD4 45 /* 0x02D */
87 #define OPC_INB_SGPIO_REGISTER 46 /* 0x02E */
88 #define OPC_INB_PCIE_DIAG_EXEC 47 /* 0x02F */
89 #define OPC_INB_SET_CONTROLLER_CONFIG 48 /* 0x030 */
90 #define OPC_INB_GET_CONTROLLER_CONFIG 49 /* 0x031 */
91 #define OPC_INB_REG_DEV 50 /* 0x032 */
92 #define OPC_INB_SAS_HW_EVENT_ACK 51 /* 0x033 */
93 #define OPC_INB_GET_DEVICE_INFO 52 /* 0x034 */
94 #define OPC_INB_GET_PHY_PROFILE 53 /* 0x035 */
95 #define OPC_INB_FLASH_OP_EXT 54 /* 0x036 */
96 #define OPC_INB_SET_PHY_PROFILE 55 /* 0x037 */
97 #define OPC_INB_KEK_MANAGEMENT 256 /* 0x100 */
98 #define OPC_INB_DEK_MANAGEMENT 257 /* 0x101 */
99 #define OPC_INB_SSP_INI_DIF_ENC_IO 258 /* 0x102 */
100 #define OPC_INB_SATA_DIF_ENC_IO 259 /* 0x103 */
103 #define OPC_OUB_ECHO 1 /* 0x001 */
104 #define OPC_OUB_RSVD 4 /* 0x004 */
105 #define OPC_OUB_SSP_COMP 5 /* 0x005 */
106 #define OPC_OUB_SMP_COMP 6 /* 0x006 */
107 #define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */
108 #define OPC_OUB_RSVD1 10 /* 0x00A */
109 #define OPC_OUB_DEREG_DEV 11 /* 0x00B */
110 #define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */
111 #define OPC_OUB_SATA_COMP 13 /* 0x00D */
112 #define OPC_OUB_SATA_EVENT 14 /* 0x00E */
113 #define OPC_OUB_SSP_EVENT 15 /* 0x00F */
114 #define OPC_OUB_RSVD2 16 /* 0x010 */
115 /* 0x11 - SMP_RECEIVED Notification removed in SPCv*/
116 #define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */
117 #define OPC_OUB_RSVD3 19 /* 0x013 */
118 #define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */
119 #define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */
120 #define OPC_OUB_GPIO_EVENT 23 /* 0x017 */
121 #define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */
122 #define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */
123 #define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */
124 #define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */
125 #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
126 #define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */
127 #define OPC_OUB_RSVD4 31 /* 0x01F */
128 #define OPC_OUB_PORT_CONTROL 32 /* 0x020 */
129 #define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */
130 #define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */
131 #define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */
132 #define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */
133 #define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */
134 #define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */
135 #define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */
136 #define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */
137 #define OPC_OUB_RSVD5 41 /* 0x029 */
138 #define OPC_OUB_HW_EVENT 1792 /* 0x700 */
139 #define OPC_OUB_DEV_HANDLE_ARRIV 1824 /* 0x720 */
140 #define OPC_OUB_THERM_HW_EVENT 1840 /* 0x730 */
141 #define OPC_OUB_SGPIO_RESP 2094 /* 0x82E */
142 #define OPC_OUB_PCIE_DIAG_EXECUTE 2095 /* 0x82F */
143 #define OPC_OUB_DEV_REGIST 2098 /* 0x832 */
144 #define OPC_OUB_SAS_HW_EVENT_ACK 2099 /* 0x833 */
145 #define OPC_OUB_GET_DEVICE_INFO 2100 /* 0x834 */
147 #define OPC_OUB_PHY_START_RESP 2052 /* 0x804 */
148 #define OPC_OUB_PHY_STOP_RESP 2053 /* 0x805 */
149 #define OPC_OUB_SET_CONTROLLER_CONFIG 2096 /* 0x830 */
150 #define OPC_OUB_GET_CONTROLLER_CONFIG 2097 /* 0x831 */
151 #define OPC_OUB_GET_PHY_PROFILE 2101 /* 0x835 */
152 #define OPC_OUB_FLASH_OP_EXT 2102 /* 0x836 */
153 #define OPC_OUB_SET_PHY_PROFILE 2103 /* 0x837 */
154 #define OPC_OUB_KEK_MANAGEMENT_RESP 2304 /* 0x900 */
155 #define OPC_OUB_DEK_MANAGEMENT_RESP 2305 /* 0x901 */
156 #define OPC_OUB_SSP_COALESCED_COMP_RESP 2306 /* 0x902 */
159 #define SSC_DISABLE_15 (0x01 << 16)
160 #define SSC_DISABLE_30 (0x02 << 16)
161 #define SSC_DISABLE_60 (0x04 << 16)
162 #define SAS_ASE (0x01 << 15)
163 #define SPINHOLD_DISABLE (0x00 << 14)
164 #define SPINHOLD_ENABLE (0x01 << 14)
165 #define LINKMODE_SAS (0x01 << 12)
166 #define LINKMODE_DSATA (0x02 << 12)
167 #define LINKMODE_AUTO (0x03 << 12)
168 #define LINKRATE_15 (0x01 << 8)
169 #define LINKRATE_30 (0x02 << 8)
170 #define LINKRATE_60 (0x04 << 8)
171 #define LINKRATE_120 (0x08 << 8)
174 #define PHY_STOP_SUCCESS 0x00
175 #define PHY_STOP_ERR_DEVICE_ATTACHED 0x1046
178 #define SAS_PHY_ANALOG_SETTINGS_PAGE 0x04
179 #define PHY_DWORD_LENGTH 0xC
182 #define THERMAL_ENABLE 0x1
183 #define THERMAL_LOG_ENABLE 0x1
184 #define THERMAL_PAGE_CODE_7H 0x6
185 #define THERMAL_PAGE_CODE_8H 0x7
190 #define SCRATCH_PAD3_ENC_DISABLED 0x00000000
191 #define SCRATCH_PAD3_ENC_DIS_ERR 0x00000001
192 #define SCRATCH_PAD3_ENC_ENA_ERR 0x00000002
193 #define SCRATCH_PAD3_ENC_READY 0x00000003
199 #define SCRATCH_PAD3_SMF_ENABLED 0
200 #define SCRATCH_PAD3_SM_MASK 0x000000F0
201 #define SCRATCH_PAD3_ERR_CODE 0x00FF0000
203 #define SEC_MODE_SMF 0x0
204 #define SEC_MODE_SMA 0x100
205 #define SEC_MODE_SMB 0x200
206 #define CIPHER_MODE_ECB 0x00000001
207 #define CIPHER_MODE_XTS 0x00000002
208 #define KEK_MGMT_SUBOP_KEYCARDUPDATE 0x4
211 #define SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04
215 #define SMP_MAX_CONN_TIMER 0xFF
216 #define STP_FRM_TIMER 0
218 #define SAS_MFD 0
233 #define SAS_MAX_AIP 0x200000
234 #define IT_NEXUS_TIMEOUT 0x7D0
237 #define CHIP_8006_PORT_RECOVERY_TIMEOUT 0x640000
241 /* Byte 0 */
288 /* Byte 0 */
336 __le32 header; /* Bits [11:0] - Message operation code */
371 u8 fis_type; /* 0xA1*/
383 u8 fis_type; /* 0x5f */
502 #define OP_BITS 0x0000FF00
503 #define ID_BITS 0x000000FF
565 #define SSP_RESCV_BIT 0x00010000
623 #define OPCODE_BITS 0x00000fff
633 /* Bits [0] - Indirect response */
780 /* B2-0 : taskAttribute */
784 /* B1-0 : reserved */
877 #define FWFLASH_IOMB_RESERVED_LEN 0x07
1000 #define TWI_DEVICE 0x0
1001 #define C_SEEPROM 0x1
1002 #define VPD_FLASH 0x4
1003 #define AAP1_RDUMP 0x5
1004 #define IOP_RDUMP 0x6
1005 #define EXPAN_ROM 0x7
1007 #define IPMode 0x80000000
1008 #define NVMD_TYPE 0x0000000F
1009 #define NVMD_STAT 0x0000FFFF
1010 #define NVMD_LEN 0xFF000000
1133 __le32 pageCode; /* 0 */
1146 #define NDS_BITS 0x0F
1147 #define PDS_BITS 0xF0
1153 #define HW_EVENT_RESET_START 0x01
1154 #define HW_EVENT_CHIP_RESET_COMPLETE 0x02
1155 #define HW_EVENT_PHY_STOP_STATUS 0x03
1156 #define HW_EVENT_SAS_PHY_UP 0x04
1157 #define HW_EVENT_SATA_PHY_UP 0x05
1158 #define HW_EVENT_SATA_SPINUP_HOLD 0x06
1159 #define HW_EVENT_PHY_DOWN 0x07
1160 #define HW_EVENT_PORT_INVALID 0x08
1161 #define HW_EVENT_BROADCAST_CHANGE 0x09
1162 #define HW_EVENT_PHY_ERROR 0x0A
1163 #define HW_EVENT_BROADCAST_SES 0x0B
1164 #define HW_EVENT_INBOUND_CRC_ERROR 0x0C
1165 #define HW_EVENT_HARD_RESET_RECEIVED 0x0D
1166 #define HW_EVENT_MALFUNCTION 0x0E
1167 #define HW_EVENT_ID_FRAME_TIMEOUT 0x0F
1168 #define HW_EVENT_BROADCAST_EXP 0x10
1169 #define HW_EVENT_PHY_START_STATUS 0x11
1170 #define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12
1171 #define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13
1172 #define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14
1173 #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15
1174 #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16
1175 #define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
1176 #define HW_EVENT_PORT_RECOVER 0x18
1177 #define HW_EVENT_PORT_RESET_TIMER_TMO 0x19
1178 #define HW_EVENT_PORT_RESET_COMPLETE 0x20
1179 #define EVENT_BROADCAST_ASYNCH_EVENT 0x21
1182 #define PORT_NOT_ESTABLISHED 0x00
1183 #define PORT_VALID 0x01
1184 #define PORT_LOSTCOMM 0x02
1185 #define PORT_IN_RESET 0x04
1186 #define PORT_3RD_PARTY_RESET 0x07
1187 #define PORT_INVALID 0x08
1193 #define IO_SUCCESS 0x00
1194 #define IO_ABORTED 0x01
1195 #define IO_OVERFLOW 0x02
1196 #define IO_UNDERFLOW 0x03
1197 #define IO_FAILED 0x04
1198 #define IO_ABORT_RESET 0x05
1199 #define IO_NOT_VALID 0x06
1200 #define IO_NO_DEVICE 0x07
1201 #define IO_ILLEGAL_PARAMETER 0x08
1202 #define IO_LINK_FAILURE 0x09
1203 #define IO_PROG_ERROR 0x0A
1205 #define IO_EDC_IN_ERROR 0x0B
1206 #define IO_EDC_OUT_ERROR 0x0C
1207 #define IO_ERROR_HW_TIMEOUT 0x0D
1208 #define IO_XFER_ERROR_BREAK 0x0E
1209 #define IO_XFER_ERROR_PHY_NOT_READY 0x0F
1210 #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10
1211 #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
1212 #define IO_OPEN_CNX_ERROR_BREAK 0x12
1213 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
1214 #define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14
1215 #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
1216 #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
1217 #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
1218 /* This error code 0x18 is not used on SPCv */
1219 #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
1220 #define IO_XFER_ERROR_NAK_RECEIVED 0x19
1221 #define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
1222 #define IO_XFER_ERROR_PEER_ABORTED 0x1B
1223 #define IO_XFER_ERROR_RX_FRAME 0x1C
1224 #define IO_XFER_ERROR_DMA 0x1D
1225 #define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E
1226 #define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
1227 #define IO_XFER_ERROR_SATA 0x20
1229 /* This error code 0x22 is not used on SPCv */
1230 #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
1231 #define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21
1232 #define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23
1233 #define IO_XFER_OPEN_RETRY_TIMEOUT 0x24
1234 /* This error code 0x25 is not used on SPCv */
1235 #define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25
1236 #define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26
1237 #define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27
1238 #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28
1239 #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
1241 /* The following error code 0x31 and 0x32 are not using (obsolete) */
1242 #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31
1243 #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
1245 #define IO_XFER_ERROR_OFFSET_MISMATCH 0x34
1246 #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35
1247 #define IO_XFER_CMD_FRAME_ISSUED 0x36
1248 #define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37
1249 #define IO_PORT_IN_RESET 0x38
1250 #define IO_DS_NON_OPERATIONAL 0x39
1251 #define IO_DS_IN_RECOVERY 0x3A
1252 #define IO_TM_TAG_NOT_FOUND 0x3B
1253 #define IO_XFER_PIO_SETUP_ERROR 0x3C
1254 #define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
1255 #define IO_DS_IN_ERROR 0x3E
1256 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
1257 #define IO_ABORT_IN_PROGRESS 0x40
1258 #define IO_ABORT_DELAYED 0x41
1259 #define IO_INVALID_LENGTH 0x42
1263 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT 0x43
1264 #define IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED 0x44
1265 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO 0x45
1266 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST 0x46
1267 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE 0x47
1268 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED 0x48
1269 #define IO_DS_INVALID 0x49
1270 #define IO_FATAL_ERROR 0x51
1272 #define IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR 0x52
1273 #define IO_XFER_DMA_ACTIVATE_TIMEOUT 0x53
1274 #define IO_XFER_ERROR_INTERNAL_CRC_ERROR 0x54
1275 #define MPI_IO_RQE_BUSY_FULL 0x55
1276 #define IO_XFER_ERR_EOB_DATA_OVERRUN 0x56
1277 #define IO_XFER_ERROR_INVALID_SSP_RSP_FRAME 0x57
1278 #define IO_OPEN_CNX_ERROR_OPEN_PREEMPTED 0x58
1280 #define MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004
1281 #define MPI_ERR_ATAPI_DEVICE_BUSY 0x1024
1283 #define IO_XFR_ERROR_DEK_KEY_CACHE_MISS 0x2040
1289 #define IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH 0x2041
1290 #define IO_XFR_ERROR_CIPHER_MODE_INVALID 0x2042
1295 #define IO_XFR_ERROR_DEK_IV_MISMATCH 0x2043
1298 #define IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR 0x2044
1301 #define IO_XFR_ERROR_INTERNAL_RAM 0x2045
1310 #define IO_XFR_ERROR_DIF_MISMATCH 0x3000
1311 #define IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001
1312 #define IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002
1313 #define IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003
1316 #define OPR_MGMT_OP_NOT_SUPPORTED 0x2060
1317 #define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061
1318 #define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062
1319 #define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063
1320 #define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064
1321 #define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL 0x2022
1322 #define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE 0x2023
1329 #define IO_ERROR_UNKNOWN_GENERIC 0x2023
1333 #define SPCv_MSGU_CFG_TABLE_UPDATE 0x001
1334 #define SPCv_MSGU_CFG_TABLE_RESET 0x002
1335 #define SPCv_MSGU_CFG_TABLE_FREEZE 0x004
1336 #define SPCv_MSGU_CFG_TABLE_UNFREEZE 0x008
1337 #define MSGU_IBDB_SET 0x00
1338 #define MSGU_HOST_INT_STATUS 0x08
1339 #define MSGU_HOST_INT_MASK 0x0C
1340 #define MSGU_IOPIB_INT_STATUS 0x18
1341 #define MSGU_IOPIB_INT_MASK 0x1C
1342 #define MSGU_IBDB_CLEAR 0x20
1344 #define MSGU_MSGU_CONTROL 0x24
1345 #define MSGU_ODR 0x20
1346 #define MSGU_ODCR 0x28
1348 #define MSGU_ODMR 0x30
1349 #define MSGU_ODMR_U 0x34
1350 #define MSGU_ODMR_CLR 0x38
1351 #define MSGU_ODMR_CLR_U 0x3C
1352 #define MSGU_OD_RSVD 0x40
1354 #define MSGU_SCRATCH_PAD_0 0x44
1355 #define MSGU_SCRATCH_PAD_1 0x48
1356 #define MSGU_SCRATCH_PAD_2 0x4C
1357 #define MSGU_SCRATCH_PAD_3 0x50
1358 #define MSGU_HOST_SCRATCH_PAD_0 0x54
1359 #define MSGU_HOST_SCRATCH_PAD_1 0x58
1360 #define MSGU_HOST_SCRATCH_PAD_2 0x5C
1361 #define MSGU_HOST_SCRATCH_PAD_3 0x60
1362 #define MSGU_HOST_SCRATCH_PAD_4 0x64
1363 #define MSGU_HOST_SCRATCH_PAD_5 0x68
1364 #define MSGU_SCRATCH_PAD_RSVD_0 0x6C
1365 #define MSGU_SCRATCH_PAD_RSVD_1 0x70
1367 #define MSGU_SCRATCHPAD1_RAAE_STATE_ERR(x) ((x & 0x3) == 0x2)
1368 #define MSGU_SCRATCHPAD1_ILA_STATE_ERR(x) (((x >> 2) & 0x3) == 0x2)
1369 #define MSGU_SCRATCHPAD1_BOOTLDR_STATE_ERR(x) ((((x >> 4) & 0x7) == 0x7) || \
1370 (((x >> 4) & 0x7) == 0x4))
1371 #define MSGU_SCRATCHPAD1_IOP0_STATE_ERR(x) (((x >> 10) & 0x3) == 0x2)
1372 #define MSGU_SCRATCHPAD1_IOP1_STATE_ERR(x) (((x >> 12) & 0x3) == 0x2)
1381 #define ODMR_MASK_ALL 0xFFFFFFFF/* mask all
1383 #define ODMR_CLEAR_ALL 0 /* clear all
1386 #define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all
1389 #define MSIX_TABLE_OFFSET 0x2000
1390 #define MSIX_TABLE_ELEMENT_SIZE 0x10
1391 #define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
1394 #define MSIX_INTERRUPT_DISABLE 0x1
1395 #define MSIX_INTERRUPT_ENABLE 0x0
1398 #define SCRATCH_PAD_RAAE_READY 0x3
1399 #define SCRATCH_PAD_ILA_READY 0xC
1400 #define SCRATCH_PAD_BOOT_LOAD_SUCCESS 0x0
1401 #define SCRATCH_PAD_IOP0_READY 0xC00
1402 #define SCRATCH_PAD_IOP1_READY 0x3000
1412 #define SCRATCH_PAD1_BOOTSTATE_MASK 0x70 /* Bit 4-6 */
1413 #define SCRATCH_PAD1_BOOTSTATE_SUCESS 0x0 /* Load successful */
1414 #define SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM 0x10 /* HDA SEEPROM */
1415 #define SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP 0x20 /* HDA BootStrap Pins */
1416 #define SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET 0x30 /* HDA Soft Reset */
1417 #define SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR 0x40 /* HDA critical error */
1418 #define SCRATCH_PAD1_BOOTSTATE_R1 0x50 /* Reserved */
1419 #define SCRATCH_PAD1_BOOTSTATE_R2 0x60 /* Reserved */
1420 #define SCRATCH_PAD1_BOOTSTATE_FATAL 0x70 /* Fatal Error */
1423 #define SCRATCH_PAD2_POR 0x00 /* power on state */
1424 #define SCRATCH_PAD2_SFR 0x01 /* soft reset state */
1425 #define SCRATCH_PAD2_ERR 0x02 /* error state */
1426 #define SCRATCH_PAD2_RDY 0x03 /* ready state */
1427 #define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW rdy for soft reset flag */
1428 #define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */
1429 #define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2
1430 Mask, bit1-0 State */
1431 #define SCRATCH_PAD2_RESERVED 0x000003FC/* Scratch Pad1
1434 #define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */
1435 #define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */
1437 /*state definition for Scratchpad Rsvd 0, Offset 0x6C, Non-fatal*/
1438 #define NON_FATAL_SPBC_LBUS_ECC_ERR 0x70000001
1439 #define NON_FATAL_BDMA_ERR 0xE0000001
1440 #define NON_FATAL_THERM_OVERTEMP_ERR 0x80000001
1443 #define MAIN_SIGNATURE_OFFSET 0x00 /* DWORD 0x00 */
1444 #define MAIN_INTERFACE_REVISION 0x04 /* DWORD 0x01 */
1445 #define MAIN_FW_REVISION 0x08 /* DWORD 0x02 */
1446 #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C /* DWORD 0x03 */
1447 #define MAIN_MAX_SGL_OFFSET 0x10 /* DWORD 0x04 */
1448 #define MAIN_CNTRL_CAP_OFFSET 0x14 /* DWORD 0x05 */
1449 #define MAIN_GST_OFFSET 0x18 /* DWORD 0x06 */
1450 #define MAIN_IBQ_OFFSET 0x1C /* DWORD 0x07 */
1451 #define MAIN_OBQ_OFFSET 0x20 /* DWORD 0x08 */
1452 #define MAIN_IQNPPD_HPPD_OFFSET 0x24 /* DWORD 0x09 */
1454 /* 0x28 - 0x4C - RSVD */
1455 #define MAIN_EVENT_CRC_CHECK 0x48 /* DWORD 0x12 */
1456 #define MAIN_EVENT_LOG_ADDR_HI 0x50 /* DWORD 0x14 */
1457 #define MAIN_EVENT_LOG_ADDR_LO 0x54 /* DWORD 0x15 */
1458 #define MAIN_EVENT_LOG_BUFF_SIZE 0x58 /* DWORD 0x16 */
1459 #define MAIN_EVENT_LOG_OPTION 0x5C /* DWORD 0x17 */
1460 #define MAIN_PCS_EVENT_LOG_ADDR_HI 0x60 /* DWORD 0x18 */
1461 #define MAIN_PCS_EVENT_LOG_ADDR_LO 0x64 /* DWORD 0x19 */
1462 #define MAIN_PCS_EVENT_LOG_BUFF_SIZE 0x68 /* DWORD 0x1A */
1463 #define MAIN_PCS_EVENT_LOG_OPTION 0x6C /* DWORD 0x1B */
1464 #define MAIN_FATAL_ERROR_INTERRUPT 0x70 /* DWORD 0x1C */
1465 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74 /* DWORD 0x1D */
1466 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78 /* DWORD 0x1E */
1467 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C /* DWORD 0x1F */
1468 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80 /* DWORD 0x20 */
1469 #define MAIN_GPIO_LED_FLAGS_OFFSET 0x84 /* DWORD 0x21 */
1470 #define MAIN_ANALOG_SETUP_OFFSET 0x88 /* DWORD 0x22 */
1472 #define MAIN_INT_VECTOR_TABLE_OFFSET 0x8C /* DWORD 0x23 */
1473 #define MAIN_SAS_PHY_ATTR_TABLE_OFFSET 0x90 /* DWORD 0x24 */
1474 #define MAIN_PORT_RECOVERY_TIMER 0x94 /* DWORD 0x25 */
1475 #define MAIN_INT_REASSERTION_DELAY 0x98 /* DWORD 0x26 */
1476 #define MAIN_MPI_ILA_RELEASE_TYPE 0xA4 /* DWORD 0x29 */
1477 #define MAIN_MPI_INACTIVE_FW_VERSION 0XB0 /* DWORD 0x2C */
1480 #define GST_GSTLEN_MPIS_OFFSET 0x00
1481 #define GST_IQ_FREEZE_STATE0_OFFSET 0x04
1482 #define GST_IQ_FREEZE_STATE1_OFFSET 0x08
1483 #define GST_MSGUTCNT_OFFSET 0x0C
1484 #define GST_IOPTCNT_OFFSET 0x10
1485 /* 0x14 - 0x34 - RSVD */
1486 #define GST_GPIO_INPUT_VAL 0x38
1487 /* 0x3c - 0x40 - RSVD */
1488 #define GST_RERRINFO_OFFSET0 0x44
1489 #define GST_RERRINFO_OFFSET1 0x48
1490 #define GST_RERRINFO_OFFSET2 0x4c
1491 #define GST_RERRINFO_OFFSET3 0x50
1492 #define GST_RERRINFO_OFFSET4 0x54
1493 #define GST_RERRINFO_OFFSET5 0x58
1494 #define GST_RERRINFO_OFFSET6 0x5c
1495 #define GST_RERRINFO_OFFSET7 0x60
1498 #define GST_MPI_STATE_UNINIT 0x00
1499 #define GST_MPI_STATE_INIT 0x01
1500 #define GST_MPI_STATE_TERMINATION 0x02
1501 #define GST_MPI_STATE_ERROR 0x03
1502 #define GST_MPI_STATE_MASK 0x07
1506 #define PSPA_PHYSTATE0_OFFSET 0x00 /* Dword V */
1507 #define PSPA_OB_HW_EVENT_PID0_OFFSET 0x04 /* DWORD V+1 */
1508 #define PSPA_PHYSTATE1_OFFSET 0x08 /* Dword V+2 */
1509 #define PSPA_OB_HW_EVENT_PID1_OFFSET 0x0C /* DWORD V+3 */
1510 #define PSPA_PHYSTATE2_OFFSET 0x10 /* Dword V+4 */
1511 #define PSPA_OB_HW_EVENT_PID2_OFFSET 0x14 /* DWORD V+5 */
1512 #define PSPA_PHYSTATE3_OFFSET 0x18 /* Dword V+6 */
1513 #define PSPA_OB_HW_EVENT_PID3_OFFSET 0x1C /* DWORD V+7 */
1514 #define PSPA_PHYSTATE4_OFFSET 0x20 /* Dword V+8 */
1515 #define PSPA_OB_HW_EVENT_PID4_OFFSET 0x24 /* DWORD V+9 */
1516 #define PSPA_PHYSTATE5_OFFSET 0x28 /* Dword V+10 */
1517 #define PSPA_OB_HW_EVENT_PID5_OFFSET 0x2C /* DWORD V+11 */
1518 #define PSPA_PHYSTATE6_OFFSET 0x30 /* Dword V+12 */
1519 #define PSPA_OB_HW_EVENT_PID6_OFFSET 0x34 /* DWORD V+13 */
1520 #define PSPA_PHYSTATE7_OFFSET 0x38 /* Dword V+14 */
1521 #define PSPA_OB_HW_EVENT_PID7_OFFSET 0x3C /* DWORD V+15 */
1522 #define PSPA_PHYSTATE8_OFFSET 0x40 /* DWORD V+16 */
1523 #define PSPA_OB_HW_EVENT_PID8_OFFSET 0x44 /* DWORD V+17 */
1524 #define PSPA_PHYSTATE9_OFFSET 0x48 /* DWORD V+18 */
1525 #define PSPA_OB_HW_EVENT_PID9_OFFSET 0x4C /* DWORD V+19 */
1526 #define PSPA_PHYSTATE10_OFFSET 0x50 /* DWORD V+20 */
1527 #define PSPA_OB_HW_EVENT_PID10_OFFSET 0x54 /* DWORD V+21 */
1528 #define PSPA_PHYSTATE11_OFFSET 0x58 /* DWORD V+22 */
1529 #define PSPA_OB_HW_EVENT_PID11_OFFSET 0x5C /* DWORD V+23 */
1530 #define PSPA_PHYSTATE12_OFFSET 0x60 /* DWORD V+24 */
1531 #define PSPA_OB_HW_EVENT_PID12_OFFSET 0x64 /* DWORD V+25 */
1532 #define PSPA_PHYSTATE13_OFFSET 0x68 /* DWORD V+26 */
1533 #define PSPA_OB_HW_EVENT_PID13_OFFSET 0x6c /* DWORD V+27 */
1534 #define PSPA_PHYSTATE14_OFFSET 0x70 /* DWORD V+28 */
1535 #define PSPA_OB_HW_EVENT_PID14_OFFSET 0x74 /* DWORD V+29 */
1536 #define PSPA_PHYSTATE15_OFFSET 0x78 /* DWORD V+30 */
1537 #define PSPA_OB_HW_EVENT_PID15_OFFSET 0x7c /* DWORD V+31 */
1541 #define IB_PROPERITY_OFFSET 0x00
1542 #define IB_BASE_ADDR_HI_OFFSET 0x04
1543 #define IB_BASE_ADDR_LO_OFFSET 0x08
1544 #define IB_CI_BASE_ADDR_HI_OFFSET 0x0C
1545 #define IB_CI_BASE_ADDR_LO_OFFSET 0x10
1546 #define IB_PIPCI_BAR 0x14
1547 #define IB_PIPCI_BAR_OFFSET 0x18
1548 #define IB_RESERVED_OFFSET 0x1C
1551 #define OB_PROPERITY_OFFSET 0x00
1552 #define OB_BASE_ADDR_HI_OFFSET 0x04
1553 #define OB_BASE_ADDR_LO_OFFSET 0x08
1554 #define OB_PI_BASE_ADDR_HI_OFFSET 0x0C
1555 #define OB_PI_BASE_ADDR_LO_OFFSET 0x10
1556 #define OB_CIPCI_BAR 0x14
1557 #define OB_CIPCI_BAR_OFFSET 0x18
1558 #define OB_INTERRUPT_COALES_OFFSET 0x1C
1559 #define OB_DYNAMIC_COALES_OFFSET 0x20
1560 #define OB_PROPERTY_INT_ENABLE 0x40000000
1562 #define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
1563 #define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
1564 /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
1565 #define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
1566 #define PCIE_EVENT_INTERRUPT 0x003044
1567 #define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
1568 #define PCIE_ERROR_INTERRUPT 0x00304C
1571 #define SPC_REG_SOFT_RESET 0x00001000
1572 #define SPCv_NORMAL_RESET_VALUE 0x1
1574 #define SPCv_SOFT_RESET_READ_MASK 0xC0
1575 #define SPCv_SOFT_RESET_NO_RESET 0x0
1576 #define SPCv_SOFT_RESET_NORMAL_RESET_OCCURED 0x40
1577 #define SPCv_SOFT_RESET_HDA_MODE_OCCURED 0x80
1578 #define SPCv_SOFT_RESET_CHIP_RESET_OCCURED 0xC0
1581 #define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
1584 /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
1585 #define SPC_REG_RESET 0x000000/* reset register */
1588 #define SPC_REG_RESET_OSSP 0x00000001
1589 #define SPC_REG_RESET_RAAE 0x00000002
1590 #define SPC_REG_RESET_PCS_SPBC 0x00000004
1591 #define SPC_REG_RESET_PCS_IOP_SS 0x00000008
1592 #define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
1593 #define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
1594 #define SPC_REG_RESET_PCS_LM 0x00000040
1595 #define SPC_REG_RESET_PCS 0x00000080
1596 #define SPC_REG_RESET_GSM 0x00000100
1597 #define SPC_REG_RESET_DDR2 0x00010000
1598 #define SPC_REG_RESET_BDMA_CORE 0x00020000
1599 #define SPC_REG_RESET_BDMA_SXCBI 0x00040000
1600 #define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
1601 #define SPC_REG_RESET_PCIE_PWR 0x00100000
1602 #define SPC_REG_RESET_PCIE_SFT 0x00200000
1603 #define SPC_REG_RESET_PCS_SXCBI 0x00400000
1604 #define SPC_REG_RESET_LMS_SXCBI 0x00800000
1605 #define SPC_REG_RESET_PMIC_SXCBI 0x01000000
1606 #define SPC_REG_RESET_PMIC_CORE 0x02000000
1607 #define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
1608 #define SPC_REG_RESET_DEVICE 0x80000000
1610 /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
1611 #define SPCV_IBW_AXI_TRANSLATION_LOW 0x001010
1613 #define MBIC_AAP1_ADDR_BASE 0x060000
1614 #define MBIC_IOP_ADDR_BASE 0x070000
1615 #define GSM_ADDR_BASE 0x0700000
1616 /* Dynamic map through Bar4 - 0x00700000 */
1617 #define GSM_CONFIG_RESET 0x00000000
1618 #define RAM_ECC_DB_ERR 0x00000018
1619 #define GSM_READ_ADDR_PARITY_INDIC 0x00000058
1620 #define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
1621 #define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
1622 #define GSM_READ_ADDR_PARITY_CHECK 0x00000038
1623 #define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
1624 #define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
1626 #define RB6_ACCESS_REG 0x6A0000
1627 #define HDAC_EXEC_CMD 0x0002
1628 #define HDA_C_PA 0xcb
1629 #define HDA_SEQ_ID_BITS 0x00ff0000
1630 #define HDA_GSM_OFFSET_BITS 0x00FFFFFF
1631 #define HDA_GSM_CMD_OFFSET_BITS 0x42C0
1632 #define HDA_GSM_RSP_OFFSET_BITS 0x42E0
1634 #define MBIC_AAP1_ADDR_BASE 0x060000
1635 #define MBIC_IOP_ADDR_BASE 0x070000
1636 #define GSM_ADDR_BASE 0x0700000
1637 #define SPC_TOP_LEVEL_ADDR_BASE 0x000000
1638 #define GSM_CONFIG_RESET_VALUE 0x00003b00
1639 #define GPIO_ADDR_BASE 0x00090000
1640 #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
1643 #define SPC_RB6_OFFSET 0x80C0
1645 #define RB6_MAGIC_NUMBER_RST 0x1234
1648 #define DEVREG_SUCCESS 0x00
1649 #define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01
1650 #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
1651 #define DEVREG_FAILURE_INVALID_PHY_ID 0x03
1652 #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
1653 #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
1654 #define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
1655 #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
1658 #define MEMBASE_II_SHIFT_REGISTER 0x1010