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/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra30-cpu-opp.dtsi10 opp-supported-hw = <0x1F 0x31FE>;
16 opp-supported-hw = <0x1F 0x0C01>;
22 opp-supported-hw = <0x1F 0x0200>;
28 opp-supported-hw = <0x1F 0x31FE>;
34 opp-supported-hw = <0x1F 0x0C01>;
40 opp-supported-hw = <0x1F 0x0200>;
46 opp-supported-hw = <0x1F 0x31FE>;
53 opp-supported-hw = <0x1F 0x0C01>;
60 opp-supported-hw = <0x1F 0x0200>;
67 opp-supported-hw = <0x1F 0x0C00>;
[all …]
/linux-6.12.1/drivers/gpu/drm/radeon/
Drs780d.h26 #define CG_SPLL_FUNC_CNTL 0x600
27 # define SPLL_RESET (1 << 0)
33 # define SPLL_FB_DIV_MASK (0xff << 2)
39 # define SPLL_SW_HILEN_MASK (0xf << 16)
42 # define SPLL_SW_LOLEN_MASK (0xf << 20)
51 #define FVTHROT_CNTRL_REG 0x3000
52 #define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0)
55 #define MINIMUM_CIP_MASK 0x1fffffe
58 #define REFRESH_RATE_DIVISOR_MASK (0x3 << 25)
64 #define FVTHROT_TARGET_REG 0x3004
[all …]
/linux-6.12.1/drivers/crypto/qce/
Dregs-v5.h11 #define REG_VERSION 0x000
12 #define REG_STATUS 0x100
13 #define REG_STATUS2 0x104
14 #define REG_ENGINES_AVAIL 0x108
15 #define REG_FIFO_SIZES 0x10c
16 #define REG_SEG_SIZE 0x110
17 #define REG_GOPROC 0x120
18 #define REG_ENCR_SEG_CFG 0x200
19 #define REG_ENCR_SEG_SIZE 0x204
20 #define REG_ENCR_SEG_START 0x208
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/mxs/
Dimx23-pinfunc.h13 #define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
14 #define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
15 #define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
16 #define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
17 #define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
18 #define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
19 #define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
20 #define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
21 #define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
22 #define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
[all …]
Dimx28-pinfunc.h13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dmarvell,pp2.yaml32 const: 0
59 '^(ethernet-)?port@[0-2]$':
92 "hifX", with X in [0..8], and "link". The names "tx-cpu0",
165 '^(ethernet-)?port@[0-2]$':
187 '^(ethernet-)?port@[0-1]$':
204 #size-cells = <0>;
206 reg = <0xf0000 0xa000>,
207 <0xc0000 0x3060>,
208 <0xc4000 0x100>,
209 <0xc5000 0x100>;
[all …]
/linux-6.12.1/drivers/net/wireless/ralink/rt2x00/
Drt2800pci.c60 for (i = 0; i < 200; i++) { in rt2800pci_mcu_status()
75 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); in rt2800pci_mcu_status()
76 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); in rt2800pci_mcu_status()
97 u32 reg = 0; in rt2800pci_eepromregister_write()
121 case 0: in rt2800pci_read_eeprom_pci()
131 eeprom.reg_data_in = 0; in rt2800pci_read_eeprom_pci()
132 eeprom.reg_data_out = 0; in rt2800pci_read_eeprom_pci()
133 eeprom.reg_data_clock = 0; in rt2800pci_read_eeprom_pci()
134 eeprom.reg_chip_select = 0; in rt2800pci_read_eeprom_pci()
139 return 0; in rt2800pci_read_eeprom_pci()
[all …]
Drt73usb.h20 #define RF5226 0x0001
21 #define RF2528 0x0002
22 #define RF5225 0x0003
23 #define RF2527 0x0004
34 #define CSR_REG_BASE 0x3000
35 #define CSR_REG_SIZE 0x04b0
36 #define EEPROM_BASE 0x0000
37 #define EEPROM_SIZE 0x0100
38 #define BBP_BASE 0x0000
39 #define BBP_SIZE 0x0080
[all …]
Drt61pci.h20 #define RT2561s_PCI_ID 0x0301
21 #define RT2561_PCI_ID 0x0302
22 #define RT2661_PCI_ID 0x0401
27 #define RF5225 0x0001
28 #define RF5325 0x0002
29 #define RF2527 0x0003
30 #define RF2529 0x0004
41 #define CSR_REG_BASE 0x3000
42 #define CSR_REG_SIZE 0x04b0
43 #define EEPROM_BASE 0x0000
[all …]
/linux-6.12.1/drivers/clk/samsung/
Dclk-gs101.c31 /* Register Offset definitions for CMU_TOP (0x1e080000) */
32 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
33 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
34 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
35 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
36 #define PLL_LOCKTIME_PLL_SPARE 0x0010
37 #define PLL_CON0_PLL_SHARED0 0x0100
38 #define PLL_CON1_PLL_SHARED0 0x0104
39 #define PLL_CON2_PLL_SHARED0 0x0108
40 #define PLL_CON3_PLL_SHARED0 0x010c
[all …]
/linux-6.12.1/arch/arm/boot/dts/marvell/
Darmada-375.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
/linux-6.12.1/drivers/pci/controller/
Dpcie-altera.c23 #define RP_TX_REG0 0x2000
24 #define RP_TX_REG1 0x2004
25 #define RP_TX_CNTRL 0x2008
26 #define RP_TX_EOP 0x2
27 #define RP_TX_SOP 0x1
28 #define RP_RXCPL_STATUS 0x2010
29 #define RP_RXCPL_EOP 0x2
30 #define RP_RXCPL_SOP 0x1
31 #define RP_RXCPL_REG0 0x2014
32 #define RP_RXCPL_REG1 0x2018
[all …]
/linux-6.12.1/drivers/scsi/qla2xxx/
Dqla_dbg.c13 * | Module Init and Probe | 0x0199 | |
14 * | Mailbox commands | 0x1206 | 0x11a5-0x11ff |
15 * | Device Discovery | 0x2134 | 0x2112-0x2115 |
16 * | | | 0x2127-0x2128 |
17 * | Queue Command and IO tracing | 0x3074 | 0x300b |
18 * | | | 0x3027-0x3028 |
19 * | | | 0x303d-0x3041 |
20 * | | | 0x302e,0x3033 |
21 * | | | 0x3036,0x3038 |
22 * | | | 0x303a |
[all …]
/linux-6.12.1/drivers/net/ethernet/hisilicon/hns/
Dhns_dsaf_reg.h10 #define HNS_DEBUG_RING_IRQ_IDX 0
46 #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x100
47 #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x180
48 #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x184
49 #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x188
50 #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C
51 #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x190
52 #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x194
53 #define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x300
54 #define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x304
[all …]
/linux-6.12.1/sound/soc/codecs/
Dwm8997.c37 static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0);
38 static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
39 static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
40 static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0);
41 static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
44 { 0x301D, 0x7B15 },
45 { 0x301B, 0x0050 },
46 { 0x305D, 0x7B17 },
47 { 0x305B, 0x0050 },
48 { 0x3001, 0x08FE },
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h26 #define ixCLIPPER_DEBUG_REG00 0x0000
27 #define ixCLIPPER_DEBUG_REG01 0x0001
28 #define ixCLIPPER_DEBUG_REG02 0x0002
29 #define ixCLIPPER_DEBUG_REG03 0x0003
30 #define ixCLIPPER_DEBUG_REG04 0x0004
31 #define ixCLIPPER_DEBUG_REG05 0x0005
32 #define ixCLIPPER_DEBUG_REG06 0x0006
33 #define ixCLIPPER_DEBUG_REG07 0x0007
34 #define ixCLIPPER_DEBUG_REG08 0x0008
35 #define ixCLIPPER_DEBUG_REG09 0x0009
[all …]
Dgfx_7_2_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_COLOR_CONTROL 0xa202
32 #define mmCB_BLEND0_CONTROL 0xa1e0
33 #define mmCB_BLEND1_CONTROL 0xa1e1
34 #define mmCB_BLEND2_CONTROL 0xa1e2
35 #define mmCB_BLEND3_CONTROL 0xa1e3
36 #define mmCB_BLEND4_CONTROL 0xa1e4
[all …]
Dgfx_7_0_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_COLOR_CONTROL 0xa202
32 #define mmCB_BLEND0_CONTROL 0xa1e0
33 #define mmCB_BLEND1_CONTROL 0xa1e1
34 #define mmCB_BLEND2_CONTROL 0xa1e2
35 #define mmCB_BLEND3_CONTROL 0xa1e3
36 #define mmCB_BLEND4_CONTROL 0xa1e4
[all …]
Dgfx_8_0_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_DCC_CONTROL 0xa109
32 #define mmCB_COLOR_CONTROL 0xa202
33 #define mmCB_BLEND0_CONTROL 0xa1e0
34 #define mmCB_BLEND1_CONTROL 0xa1e1
35 #define mmCB_BLEND2_CONTROL 0xa1e2
36 #define mmCB_BLEND3_CONTROL 0xa1e3
[all …]
/linux-6.12.1/drivers/media/i2c/
Dar0521.c31 #define AR0521_MIN_X_ADDR_START 0u
32 #define AR0521_MIN_Y_ADDR_START 0u
46 #define AR0521_ANA_GAIN_MIN 0x00
47 #define AR0521_ANA_GAIN_MAX 0x3f
48 #define AR0521_ANA_GAIN_STEP 0x01
49 #define AR0521_ANA_GAIN_DEFAULT 0x00
52 #define AR0521_REG_VT_PIX_CLK_DIV 0x0300
53 #define AR0521_REG_FRAME_LENGTH_LINES 0x0340
55 #define AR0521_REG_CHIP_ID 0x3000
56 #define AR0521_REG_COARSE_INTEGRATION_TIME 0x3012
[all …]
/linux-6.12.1/include/video/
Dpm3fb.h19 #define PM3ResetStatus 0x0000
20 #define PM3IntEnable 0x0008
21 #define PM3IntFlags 0x0010
22 #define PM3InFIFOSpace 0x0018
23 #define PM3OutFIFOWords 0x0020
24 #define PM3DMAAddress 0x0028
25 #define PM3DMACount 0x0030
26 #define PM3ErrorFlags 0x0038
27 #define PM3VClkCtl 0x0040
28 #define PM3TestRegister 0x0048
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_3_1_4_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000
33 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001
34 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002
35 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003
36 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004
37 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005
38 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006
39 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007
40 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008
[all …]
Ddpcs_4_2_0_offset.h27 // base address: 0x0
28 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
30 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
35 // base address: 0x360
36 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
43 // base address: 0x6c0
44 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
46 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
51 // base address: 0xa20
[all …]
Ddpcs_4_2_2_offset.h14 // base address: 0x0
15 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
17 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
22 // base address: 0x360
23 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
25 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
30 // base address: 0x6c0
31 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
33 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
38 // base address: 0xa20
[all …]
Ddpcs_4_2_3_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
34 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
39 // base address: 0x360
40 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
42 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
47 // base address: 0x6c0
48 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
50 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
55 // base address: 0xa20
[all …]

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